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1. 发明授权

US07328317B2 Memory controller and method for optimized read/modify/write performance 有权
标题翻译：用于优化读/写/写性能的内存控制器和方法
公开(公告)号：US07328317B2
公开(公告)日：2008-02-05
申请号：US10970400
申请日：2004-10-21
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

2. 发明授权

US07908443B2 Memory controller and method for optimized read/modify/write performance 失效
标题翻译：用于优化读/写/写性能的内存控制器和方法
公开(公告)号：US07908443B2
公开(公告)日：2011-03-15
申请号：US12136750
申请日：2008-06-10
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

3. 发明授权

US07475202B2 Memory controller and method for optimized read/modify/write performance 有权
标题翻译：用于优化读/写/写性能的内存控制器和方法
公开(公告)号：US07475202B2
公开(公告)日：2009-01-06
申请号：US11779277
申请日：2007-07-18
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

4. 发明申请

US20090024808A1 MEMORY CONTROLLER AND METHOD FOR OPTIMIZED READ/MODIFY/WRITE PERFORMANCE 审中-公开
标题翻译：用于优化读/修/写性能的存储器控制器和方法
公开(公告)号：US20090024808A1
公开(公告)日：2009-01-22
申请号：US12136752
申请日：2008-06-10
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F9/3004
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。这些实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

5. 发明申请

US20090024807A1 MEMORY CONTROLLER AND METHOD FOR OPTIMIZED READ/MODIFY/WRITE PERFORMANCE 失效
公开(公告)号：US20090024807A1
公开(公告)日：2009-01-22
申请号：US12136750
申请日：2008-06-10
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

6. 发明授权

US07707463B2 Implementing directory organization to selectively optimize performance or reliability 有权
标题翻译：实施目录组织以选择性地优化性能或可靠性
公开(公告)号：US07707463B2
公开(公告)日：2010-04-27
申请号：US11290894
申请日：2005-11-30
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
IPC分类号： G06F11/00
CPC分类号： G06F11/1064 , G06F12/082
摘要： A method, and apparatus are provided for implementing a directory organization to selectively optimize performance or reliability in a computer system. A directory includes a user selected operational modes including a performance mode and a reliability mode. In the reliability mode, more directory bits are used for error correction and detection. In the performance mode, reclaimed directory bits not used for error correction and detection are used for more associativity.
摘要翻译：提供了一种用于实现目录组织以选择性地优化计算机系统中的性能或可靠性的方法和装置。目录包括用户选择的操作模式，包括演奏模式和可靠性模式。在可靠性模式下，更多的目录位用于纠错和检测。在性能模式下，不用于纠错和检测的回收目录位用于更多的关联性。

7. 发明授权

US07703063B2 Implementing memory read data eye stretcher 失效
标题翻译：实现内存读数据眼担架
公开(公告)号：US07703063B2
公开(公告)日：2010-04-20
申请号：US11840394
申请日：2007-08-17
申请人： William Paul Hovis , Paul W. Rudrud
发明人： William Paul Hovis , Paul W. Rudrud
IPC分类号： G06F17/50
CPC分类号： G11C11/4076 , G11C7/1042 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C11/4093
摘要： A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.
摘要翻译：实现高速的方法和数据接收装置，例如双倍数据速率（DDR），存储器读数据眼担架。执行改变参考电平以增加数据眼睛的大小。使用先前数据状态的知识来调整被锁存的当前数据的参考电平，使得数据眼睛被最大化。

8. 发明授权

US07603528B2 Memory device verification of multiple write operations 失效
标题翻译：多个写入操作的内存设备验证
公开(公告)号：US07603528B2
公开(公告)日：2009-10-13
申请号：US10961745
申请日：2004-10-08
申请人： William Hugh Cochran , William Paul Hovis , Paul Rudrud
发明人： William Hugh Cochran , William Paul Hovis , Paul Rudrud
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F12/0804 , G06F12/084
摘要： Verification operations are utilized to effectively verify multiple associated write operations. A verification operation may be initiated after the issuance of a plurality of write operations that initiate the storage of data to a memory storage device, and may be configured to verify only a subset of the data written to the memory storage device by the plurality of write operations. As a result, verification operations are not required to be performed after each write operation, and consequently, the number of verification operations, and thus the processing and communication bandwidth consumed thereby, can be substantially reduced.
摘要翻译：利用验证操作来有效地验证多个关联的写入操作。可以在发出数据到存储器存储设备的多个写入操作的发出之后启动验证操作，并且可以被配置为仅通过多个写入验证写入存储器存储设备的数据的子集操作。结果，在每次写入操作之后不需要执行验证操作，因此可以显着减少验证操作的数量，从而可以大大减少由此消耗的处理和通信带宽。

9. 发明授权

US07526692B2 Diagnostic interface architecture for memory device 有权
标题翻译：内存设备的诊断接口架构
公开(公告)号：US07526692B2
公开(公告)日：2009-04-28
申请号：US10955735
申请日：2004-09-30
申请人： John Michael Borkenhagen , William Paul Hovis , James Anthony Marcella , Paul Rudrud
发明人： John Michael Borkenhagen , William Paul Hovis , James Anthony Marcella , Paul Rudrud
IPC分类号： G01R31/28
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/5602
摘要： A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.
摘要翻译：用于存储器设备的诊断接口架构在一个方面支持通常与从存储器件读取数据和/或将数据写入存储器件一起使用的一个或多个动态可重新配置的功能互连。动态可重构功能互连能够被配置为以功能或诊断模式操作，由此在诊断模式中，这种互连可以用于传送诊断信息以支持一个或多个诊断操作。诊断接口架构还可以支持给定存储器设备中的多个诊断接口，其中至少一个这样的诊断接口能够响应于另一诊断接口中的故障被选择性地启用。

10. 发明授权

US07517764B2 Bulk FinFET device 有权
标题翻译：散装FinFET器件
公开(公告)号：US07517764B2
公开(公告)日：2009-04-14
申请号：US11427486
申请日：2006-06-29
申请人： Roger Allen Booth, Jr. , William Paul Hovis , Jack Allan Mandelman
发明人： Roger Allen Booth, Jr. , William Paul Hovis , Jack Allan Mandelman
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。该结构包括在finFET的硅体和衬底之间的体接触。

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