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1. 发明申请

US20130145190A1 DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM 有权
标题翻译：数据处理设备和数据处理系统
公开(公告)号：US20130145190A1
公开(公告)日：2013-06-06
申请号：US13816479
申请日：2010-08-26
申请人： Mamoru Sakugawa , Masamichi Fujito , Jun Setogawa , Masaru Takahashi , Shinsuke Yoshimura
发明人： Mamoru Sakugawa , Masamichi Fujito , Jun Setogawa , Masaru Takahashi , Shinsuke Yoshimura
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3206 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode.
摘要翻译：中央处理单元根据用户程序设置数据处理装置要操作的以下哪种模式。高速运行模式允许在外部电源电压相对较高的第一范围内运行。宽电压范围操作模式允许在外部电源电压包括第一范围和相对低的电压范围的第二范围内操作，并且宽电压范围操作模式中的第一时钟的频率的上限低于在高速运行模式中的第一时钟的频率的上限。在低功耗操作模式中，第一时钟的频率低于高速操作模式中的第一时钟的频率和宽电压范围操作模式下的第一时钟的频率。

2. 发明授权

US08017986B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08017986B2
公开(公告)日：2011-09-13
申请号：US12718111
申请日：2010-03-05
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

3. 发明授权

US07957195B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07957195B2
公开(公告)日：2011-06-07
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

4. 发明授权

US07414283B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07414283B2
公开(公告)日：2008-08-19
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

5. 发明申请

US20070040595A1 Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20070040595A1
公开(公告)日：2007-02-22
申请号：US11586672
申请日：2006-10-26
申请人： Ayako Kakuda , Masamichi Fujito
发明人： Ayako Kakuda , Masamichi Fujito
IPC分类号： H03H11/26
CPC分类号： G11C7/222 , G11C7/04 , G11C7/06 , H03K5/133 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A delay circuit includes a constant current source, a delay stage, and a compensating circuit. The delay circuit may compensate for a variation in a delay characteristic of the delay stage due to a variation in temperature, supply voltage and/or process.
摘要翻译：延迟电路包括恒流源，延迟级和补偿电路。延迟电路可以由于温度，电源电压和/或过程的变化而补偿延迟级的延迟特性的变化。

6. 发明授权

US06963507B2 Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory 有权
公开(公告)号：US06963507B2
公开(公告)日：2005-11-08
申请号：US10419228
申请日：2003-04-21
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
IPC分类号： G11C16/02 , G11C8/02 , G11C16/12 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/12 , G11C2216/14
摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

7. 发明申请

US20100157689A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100157689A1
公开(公告)日：2010-06-24
申请号：US12718111
申请日：2010-03-05
申请人： TOSHIHIRO TANAKA , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： TOSHIHIRO TANAKA , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： G11C16/06 , H01L29/788 , G11C16/04
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

8. 发明授权

US07700992B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07700992B2
公开(公告)日：2010-04-20
申请号：US12142566
申请日：2008-06-19
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

9. 发明申请

US20100080058A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100080058A1
公开(公告)日：2010-04-01
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

10. 发明申请

US20080089146A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080089146A1
公开(公告)日：2008-04-17
申请号：US11869144
申请日：2007-10-09
申请人： Masamichi FUJITO , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi FUJITO , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞格的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并且具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

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