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1. 发明授权

US06239631B1 Integrated circuit device with input buffer capable of correspondence with highspeed clock 有权
标题翻译：具有与高速时钟对应的输入缓冲器的集成电路器件
公开(公告)号：US06239631B1
公开(公告)日：2001-05-29
申请号：US09377104
申请日：1999-08-19
申请人： Shinya Fujioka , Hiroyoshi Tomita
发明人： Shinya Fujioka , Hiroyoshi Tomita
IPC分类号： H03L700
CPC分类号： G11C7/1093 , G06F5/06 , G11C7/1087 , G11C7/222 , H03L7/00
摘要： One aspect of the present invention is characterized in that an input buffer circuit constitutes either 2 sets, or a plurality of sets relative to 1 input signal, either a pair of complementary internal clocks, or a plurality of internal clocks are generated by frequency-dividing a supplied clock inside the integrated circuit device, and input signals are received and latched either in synchronization with a pair of complementary clocks, or in synchronization with a plurality of clocks in accordance with an input buffer of either 2 sets or a plurality of sets. The output of input buffers of either 2 sets or a plurality of sets are combined by a combining circuit, and supplied internally. An H level or an L level period is set for the internally-generated internal clock so that outputs from the various input buffers are not in contention with one another. According to the present invention, the operation of input buffers of a plurality of sets are synchronized with internal clocks of a slower speed than a supplied clock, thus enabling the reliable receive of input signals.
摘要翻译：本发明的一个方面的特征在于，输入缓冲电路构成2组或相对于1个输入信号的多组，一对互补的内部时钟或多个内部时钟通过分频产生集成电路器件内的提供的时钟和输入信号可以与一对互补时钟同步地接收和锁存，或者根据两组或多组的输入缓冲器与多个时钟同步地被接收和锁存。 2组或多组的输入缓冲器的输出由组合电路组合，并在内部提供。为内部产生的内部时钟设置一个H电平或一个L电平周期，使得各种输入缓冲器的输出不会相互竞争。根据本发明，多个组的输入缓冲器的操作与比所提供的时钟慢的内部时钟同步，因此能够可靠地接收输入信号。

2. 发明申请

US20120225531A1 SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CAPACITOR 有权
标题翻译：半导体器件，包括具有电容器的存储器单元
公开(公告)号：US20120225531A1
公开(公告)日：2012-09-06
申请号：US13473242
申请日：2012-05-16
申请人： Hiroyuki Ogawa , Hiroyoshi Tomita , Masato Takita
发明人： Hiroyuki Ogawa , Hiroyoshi Tomita , Masato Takita
IPC分类号： H01L21/02
CPC分类号： H01L27/0207 , G11C5/063 , G11C7/02 , G11C7/18 , G11C11/4097 , H01L27/1085 , H01L27/10885 , H01L27/10897
摘要： A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.
摘要翻译：半导体器件包括半导体衬底; 存储单元阵列，包括形成在所述半导体衬底上并在所述半导体衬底的表面上沿第一方向和第二方向布置成矩阵的多个存储单元; 多个读出放大器，形成在半导体衬底上并包括第一读出放大器和第二读出放大器; 以及沿着存储单元阵列上方的第一方向延伸并沿第二方向并排布置的多个位线，其中多个位线包括形成在第一布线层中的第一位线对和第二位线形成在位于第一布线层上方的第二布线层中。

3. 发明授权

US07723796B2 Semiconductor device with current mirror circuit having two transistors of identical characteristics 有权
标题翻译：具有电流镜电路的半导体器件具有两个相同特性的晶体管
公开(公告)号：US07723796B2
公开(公告)日：2010-05-25
申请号：US11902568
申请日：2007-09-24
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： H01L23/62
CPC分类号： G05F3/262 , H01L29/4238
摘要： A semiconductor device includes a current-mirror circuit including a first ring-shape gate, a second ring-shape gate, a first diffusion layer formed around the first ring-shape gate and the second ring-shape gate, a second diffusion layer formed inside the first ring-shape gate, a third diffusion layer formed inside the second ring-shape gate, an interconnect line electrically connecting the first ring-shape gate and the second ring-shape gate to a same potential, and an STI area formed around the first diffusion layer, wherein a first transistor corresponding to the first ring-shape gate and a second transistor corresponding to the second ring-shape gate constitute the current-mirror circuit, wherein gates of dummy transistors that do not function as transistors are situated between the STI area and the first and second ring-shape gates, and are arranged both in a first direction and in a second direction substantially perpendicular to the first direction.
摘要翻译：一种半导体器件包括：电流镜电路，包括第一环形栅极，第二环形栅极，形成在第一环状栅极和第二环形栅极周围的第一扩散层，第二扩散层，第一环形栅极，形成在第二环形栅极内部的第三扩散层，将第一环形栅极和第二环形栅极电连接到相同电位的互连线，以及形成在第二环形栅极周围的STI区域第一扩散层，其中对应于第一环形栅极的第一晶体管和对应于第二环形栅极的第二晶体管构成电流镜电路，其中不用作晶体管的虚拟晶体管的栅极位于 STI区域和第一和第二环形门，并且布置在基本上垂直于第一方向的第一方向和第二方向上。

4. 发明授权

US07539042B2 Semiconductor device and fabrication method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07539042B2
公开(公告)日：2009-05-26
申请号：US11783318
申请日：2007-04-09
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： G11C11/24 , G11C7/00 , G11C8/00
CPC分类号： G11C11/4074 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2207/2254 , H01L27/0207 , H01L27/10829
摘要： The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit for recording a set value of a back bias potential to be applied to a back gate of a cell transistor and a second unit for generating a back bias potential based on the set value of the back bias potential recorded in the first unit and supplying the generated back bias potential to the back gate, wherein when a threshold of a MOSFET which has a structure identical to the cell transistor and which has been fabricated in the same process as the cell transistor is greater than a target value which the cell transistor should have, a value shallower than the back bias potential for the target value is recorded in the second unit.
摘要翻译：本发明抑制由于MOSFET的阈值的偏差引起的DRAM的刷新故障。 DRAM具有第一单元，用于记录要施加到单元晶体管的背栅的背偏置电位的设定值，以及用于产生背偏电位的第二单元，其基于记录在所述单元晶体管中的背偏电位的设定值第一单元并将所产生的反向偏置电位提供给所述后栅极，其中当具有与所述单元晶体管相同的并且已经以与所述单元晶体管相同的工艺制造的结构的MOSFET的阈值大于目标值时，单元晶体管应当具有比目标值的背偏电位浅的值被记录在第二单元中。

5. 发明授权

US07109775B2 Delay circuit having reduced power supply voltage dependency 有权
标题翻译：具有降低的电源电压依赖性的延迟电路
公开(公告)号：US07109775B2
公开(公告)日：2006-09-19
申请号：US11110685
申请日：2005-04-21
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , H03K5/133 , H03K2005/00071
摘要： A delay circuit includes: an input signal line (IN) through which an input signal is inputted; a capacitor (106) charged with and discharging electric charge; a first switch (101) connected to the input signal line and operating according to the input signal when the capacitor is to be charged with electric charge; a second switch (102) connected to the input signal line and operating according to the input signal when the electric charge is to be discharged from the capacitor; and a comparison circuit (107) comparing a voltage of the capacitor and a reference voltage to output a delay signal of the input signal.
摘要翻译：延迟电路包括：输入信号线（IN），输入信号经输入信号线输入; 充电并放电的电容器（106）第一开关（101），连接到所述输入信号线，并且当所述电容器要被充电时根据所述输入信号进行操作; 第二开关（102），连接到输入信号线，并且当电荷从电容器放电时，根据输入信号进行操作; 以及将电容器的电压和参考电压进行比较以输出输入信号的延迟信号的比较电路（107）。

6. 发明授权

US06973001B1 Semiconductor integrated circuit capable of adjusting the operation timing of an internal circuit based on operating environments 失效
标题翻译：能够根据操作环境调整内部电路的动作时序的半导体集成电路
公开(公告)号：US06973001B1
公开(公告)日：2005-12-06
申请号：US11036393
申请日：2005-01-18
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： G06F1/10 , G11C7/04 , G11C7/10 , G11C11/407 , G11C11/4076 , H03K3/037 , H03K3/356 , H03K5/00 , H03K5/13 , H03K5/135
CPC分类号： H03K5/135 , G11C7/04 , G11C7/1072 , G11C7/222 , H03K5/133 , H03K2005/00234
摘要： The gates of each pair of second transistors receive a pair of delayed timing signals whose rising and falling edges are adjacent to each other, respectively, and gradually discharge the charges at a first node pre-charged to a first power supply voltage. The discharge speed varies depending on the threshold voltage, operating temperature, and power supply voltage of the transistors. A plurality of detection circuits operates at timings different from each other to detect the voltage at the first node as logic values. A selector selects any one of the second timing signals depending on a detection result provided by the detection circuit. An internal circuit operates in synchronization with the second timing signal selected. Accordingly, the operation timing of the internal circuit can be optimally adjusted in response to a change in operating environments. This allows the improvement in operation margin of the semiconductor integrated circuit.
摘要翻译：每对第二晶体管的栅极分别接收一对延迟定时信号，其上升沿和下降沿分别相邻，并且将预充电的第一节点处的电荷逐渐放电至第一电源电压。放电速度根据晶体管的阈值电压，工作温度和电源电压而变化。多个检测电路在彼此不同的定时运行，以将第一节点处的电压检测为逻辑值。选择器根据由检测电路提供的检测结果来选择第二定时信号中的任何一个。内部电路与所选择的第二定时信号同步工作。因此，可以根据操作环境的变化来最佳地调整内部电路的操作定时。这允许改善半导体集成电路的操作裕度。

7. 发明授权

US06671787B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US06671787B2
公开(公告)日：2003-12-30
申请号：US09264672
申请日：1999-03-09
申请人： Tatsuya Kanda , Hiroyoshi Tomita
发明人： Tatsuya Kanda , Hiroyoshi Tomita
IPC分类号： G06F1200
CPC分类号： G11C7/1087 , G11C7/1021 , G11C7/1039 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C29/14
摘要： The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.
摘要翻译：本发明涉及一种与外部时钟同步写入或读取数据的SDRAM及其控制方法，其目的在于提供一种半导体存储器件及其方法，该半导体存储器件及其方法可以容易地由具有传输类型与外部时钟的上升沿和下降沿同步传输数据。半导体存储器件具有写入放大器控制部分14和I / O数据缓冲器/寄存器22，作为对应于DDR类型和SDR类型的数据传输类型的数据传输电路。此外，模式寄存器28形成为用作切换信号以将数据传输电路切换为DDR类型或SDR类型。

8. 发明授权

US06373783B1 Semiconductor integrated circuit, method of controlling the same, and variable delay circuit 有权
公开(公告)号：US06373783B1
公开(公告)日：2002-04-16
申请号：US09587296
申请日：2000-06-05
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： G11C800
CPC分类号： G11C8/18
摘要： In performing a read operation or a write operation in a memory cell, a row control circuit is first operated to activate a word line. Subsequently, a command control circuit receives a column operation command in synchronization with a clock signal so as to operate a column control circuit. Here, under the control of a timing adjusting circuit, the column control circuit starts operating a predetermined delay time after the reception of the column operation command. By delaying the operation of the column control circuit, the read operation or the write operation in the memory cell can be performed at the optimum timing corresponding to the operating timing of an internal circuit independent of the cycle of the clock signal. As a result, the number of times in receiving commands per unit time can be increased to enhance the bus occupation rate of data. Since the column control circuit is operated at the optimum timing corresponding to the operating timing of the internal circuit, a read cycle time and a write cycle time can be shortened.

9. 发明授权

US06288585B1 Semiconductor device using external power voltage for timing sensitive signals 有权
标题翻译：半导体器件使用外部电源电压进行时序敏感信号
公开(公告)号：US06288585B1
公开(公告)日：2001-09-11
申请号：US09535745
申请日：2000-03-27
申请人： Yoshihide Bando , Nobutaka Taniguchi , Hiroyoshi Tomita , Kota Hara , Naoharu Shinozaki
发明人： Yoshihide Bando , Nobutaka Taniguchi , Hiroyoshi Tomita , Kota Hara , Naoharu Shinozaki
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.
摘要翻译：接收稳定的外部电源电压的半导体器件包括产生内部降低的电源电压的降压产生电路，基于内部降低的电源电压进行操作的输入电路，使内部降低的电源电压波动，控制电路，其产生内部时钟信号;输出电路，其响应于内部时钟信号以输出定时将数据信号输出到设备的外部;时钟传送电路，其传送来自时钟控制电路的内部时钟信号到输出电路，并且基于外部电源电压进行操作，以使得输出定时基本上不受内部降低的功率电压的波动的影响。

10. 发明授权

US06252804B1 Semiconductor integrated circuit, and method of controlling same 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US06252804B1
公开(公告)日：2001-06-26
申请号：US09629619
申请日：2000-07-31
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： G11C1140
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1072 , G11C7/1078
摘要： A semiconductor integrated circuit comprising memory cells and a holding unit. The holding unit holds write data to the memory cell and mask information for masking a predetermined bit or bits of the write data, both supplied corresponding to a write command, as held write data and held mask information. On receiving a next write command, the semiconductor integrated circuit masks held write data in accordance with held mask information and writes the resultant to the memory cell. The holding unit holds next write data and next mask information supplied corresponding to this write command as held write data and held mask information. That is, the held write data and the held mask information are rewritten. Thereby, the semiconductor integrated circuit which writes write data previously accepted upon the reception of a next write command can mask the write data.
摘要翻译：一种包括存储单元和保持单元的半导体集成电路。保持单元将写入数据保存到存储单元，并且掩蔽信息，用于屏蔽对应于写入命令的写入数据的预定位或位，作为保持写入数据和保持的掩码信息。在接收到下一个写入命令时，半导体集成电路根据所保持的掩码信息掩蔽保持写入数据，并将结果写入存储单元。保持单元保持与该写入命令相对应的下一个写入数据和下一个掩模信息作为保持的写入数据和保持的掩码信息。也就是说，保持的写入数据和保持的掩码信息被重写。由此，在接收下一个写入命令时写入预先接受的写入数据的半导体集成电路可以掩蔽写入数据。

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