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1. 发明授权

US07236035B2 Semiconductor device adapted to minimize clock skew 有权
标题翻译：半导体器件适合于最小化时钟偏移
公开(公告)号：US07236035B2
公开(公告)日：2007-06-26
申请号：US10990537
申请日：2004-11-18
申请人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
发明人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.
摘要翻译：第一个逻辑电路的电源电压被控制。第二逻辑电路响应于外部时钟信号而工作。调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

2. 发明申请

US20060061401A1 Semiconductor device adapted to minimize clock skew 有权
标题翻译：半导体器件适合于最小化时钟偏移
公开(公告)号：US20060061401A1
公开(公告)日：2006-03-23
申请号：US10990537
申请日：2004-11-18
申请人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
发明人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.
摘要翻译：第一个逻辑电路的电源电压被控制。第二逻辑电路响应于外部时钟信号而工作。调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

3. 发明申请

US20060198198A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060198198A1
公开(公告)日：2006-09-07
申请号：US11342617
申请日：2006-01-31
申请人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
发明人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C5/147
摘要： According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.
摘要翻译：根据本发明，提供了一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

4. 发明授权

US07417489B2 Semiconductor integrated circuit having controller controlling the change rate of power voltage 有权
标题翻译：具有控制器控制电源电压变化率的半导体集成电路
公开(公告)号：US07417489B2
公开(公告)日：2008-08-26
申请号：US11342617
申请日：2006-01-31
申请人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
发明人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
IPC分类号： G05F1/10
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.
摘要翻译：一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

5. 发明授权

US07551019B2 Semiconductor integrated circuit and source voltage/substrate bias control circuit 失效
标题翻译：半导体集成电路和源极电压/衬底偏置控制电路
公开(公告)号：US07551019B2
公开(公告)日：2009-06-23
申请号：US11764605
申请日：2007-06-18
申请人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
发明人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G05F3/16 , H03L1/00
CPC分类号： G05F3/205
摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

6. 发明申请

US20050093611A1 Semiconductor integrated circuit and source voltage/substrate bias control circuit 有权
标题翻译：半导体集成电路和源极电压/衬底偏置控制电路
公开(公告)号：US20050093611A1
公开(公告)日：2005-05-05
申请号：US10899004
申请日：2004-07-27
申请人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
发明人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： H01L27/04 , G05F3/20 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K3/01 , H03K17/00
CPC分类号： G05F3/205
摘要： A semiconductor integrated circuit comprises a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generating circuit applying substrate biases to individual said well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：半导体集成电路包括半导体衬底; 多个阱区，形成在所述半导体衬底的一个表面上并彼此电隔离; 形成在所述阱区中的多个MOS晶体管; 以及衬底偏置产生电路，其基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差将单独的所述阱区域施加衬底偏置，以使各MOS晶体管的阈值电压与正常阈值电压一致。

7. 发明申请

US20070236276A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND SOURCE VOLTAGE/SUBSTRATE BIAS CONTROL CIRCUIT 失效
标题翻译：半导体集成电路和源极电压/基极偏置控制电路
公开(公告)号：US20070236276A1
公开(公告)日：2007-10-11
申请号：US11764605
申请日：2007-06-18
申请人： Tetsuya FUJITA , Mototsugu Hamada , Hiroyuki Hara
发明人： Tetsuya FUJITA , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： H01L29/94
CPC分类号： G05F3/205
摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

8. 发明授权

US07397271B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07397271B2
公开(公告)日：2008-07-08
申请号：US11502572
申请日：2006-08-11
申请人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
发明人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17728 , H03K19/1778
摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal; a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state; and a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state.
摘要翻译：半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。所述逻辑单元中的至少一个具有：包括MIS晶体管的标准单元，所述标准单元包括输入来自前一级的输出信号的输入端作为输入信号和输出端，所述标准单元执行基于所述输入信号进行预定的逻辑运算，并输出所述逻辑运算的结果作为来自所述输出端子的输出信号; 设置在标准单元的输出端子与第一电源电压之间的第一导电型第一MIS晶体管，所述第一MIS晶体管包括输入电路控制信号的控制端子和提供电路控制信号的第一MIS晶体管基于电路控制信号向标准单元的输出端施加第一电源电压，以使标准单元进入操作停止状态; 以及设置在所述标准单元和第二电源电压之间的第二导电型第二MIS晶体管，所述第二MIS晶体管包括输入所述电路控制信号的控制端子，所述第二MIS晶体管切断漏电流的基于电路控制信号的标准单元中的MIS晶体管，以使标准单元进入操作停止状态。

9. 发明申请

US20080080231A1 NONVOLATILE LATCH CIRCUIT AND NONVOLATILE FLIP-FLOP CIRCUIT 有权
标题翻译：非易失性电路和非易失性FLIP-FLOP电路
公开(公告)号：US20080080231A1
公开(公告)日：2008-04-03
申请号：US11848864
申请日：2007-08-31
申请人： Keiko Abe , Takahiro Hirai , Shiho Nakamura , Hirofumi Morise , Mototsugu Hamada
发明人： Keiko Abe , Takahiro Hirai , Shiho Nakamura , Hirofumi Morise , Mototsugu Hamada
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C14/0081
摘要： A nonvolatile latch circuit includes: a first gate part controlling to load or intercept an input signal based on a gate signal; a first logic gate functioning as an inverter or a gate outputting a constant voltage in response to the first control signal; a second logic gate functioning as an inverter or a gate outputting the constant voltage in response to the first control signal; a second gate part controlling to load or intercept the output of the second logic gate based on an inverted signal of the gate signal and sends the output of the second logic gate to an first input terminal of the first logic gate; and first and second injection type MTJ elements provided between the driving power supply and the first and second logic gates and changing in resistance depending upon a current flow direction.
摘要翻译：非易失性锁存电路包括：第一栅极部分，其基于栅极信号控制输入信号的加载或截取; 用作反相器的第一逻辑门或响应于第一控制信号输出恒定电压的栅极; 用作反相器的第二逻辑门或响应于第一控制信号输出恒定电压的栅极; 第二栅极部分，用于基于所述栅极信号的反相信号来加载或截取所述第二逻辑门的输出，并将所述第二逻辑门的输出发送到所述第一逻辑门的第一输入端; 以及设置在驱动电源和第一和第二逻辑门之间的第一和第二注入型MTJ元件，并根据电流流动方向改变电阻。

10. 发明申请

US20070296485A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070296485A1
公开(公告)日：2007-12-27
申请号：US11758394
申请日：2007-06-05
申请人： Mitsuyuki ASHIDA , Mototsugu Hamada
发明人： Mitsuyuki ASHIDA , Mototsugu Hamada
IPC分类号： H03H11/40
CPC分类号： H03K19/0013
摘要： A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.
摘要翻译：半导体器件具有作为第一导电型MOS晶体管的主晶体管，并且漏极连接到第一电位; 连接在所述主晶体管的源极和第二电位之间的第一开关电路; 作为第一导电型MOS晶体管的虚设晶体管，其源极也用作所述主晶体管的源极; 以及连接在所述虚拟晶体管的漏极与所述第一电位或所述第二电位之间的第二开关电路。

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