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1. 发明授权

US08134404B2 Semiconductor device that degrades leak current of a transistor 有权
标题翻译：降低晶体管漏电流的半导体器件
公开(公告)号：US08134404B2
公开(公告)日：2012-03-13
申请号：US12692387
申请日：2010-01-22
申请人： Mitsuyuki Ashida , Mototsugu Hamada
发明人： Mitsuyuki Ashida , Mototsugu Hamada
IPC分类号： H03K3/01
CPC分类号： H03K19/0013
摘要： A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.
摘要翻译：半导体器件具有作为第一导电型MOS晶体管的主晶体管，并且漏极连接到第一电位; 连接在所述主晶体管的源极和第二电位之间的第一开关电路; 作为第一导电型MOS晶体管的虚设晶体管，其源极也用作所述主晶体管的源极; 以及连接在所述虚拟晶体管的漏极与所述第一电位或所述第二电位之间的第二开关电路。

2. 发明申请

US20070296485A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070296485A1
公开(公告)日：2007-12-27
申请号：US11758394
申请日：2007-06-05
申请人： Mitsuyuki ASHIDA , Mototsugu Hamada
发明人： Mitsuyuki ASHIDA , Mototsugu Hamada
IPC分类号： H03H11/40
CPC分类号： H03K19/0013
摘要： A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.
摘要翻译：半导体器件具有作为第一导电型MOS晶体管的主晶体管，并且漏极连接到第一电位; 连接在所述主晶体管的源极和第二电位之间的第一开关电路; 作为第一导电型MOS晶体管的虚设晶体管，其源极也用作所述主晶体管的源极; 以及连接在所述虚拟晶体管的漏极与所述第一电位或所述第二电位之间的第二开关电路。

3. 发明申请

US20120243583A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20120243583A1
公开(公告)日：2012-09-27
申请号：US13237050
申请日：2011-09-20
申请人： Mitsuyuki Ashida , Hideaki Majima
发明人： Mitsuyuki Ashida , Hideaki Majima
IPC分类号： H04B1/54
CPC分类号： H04B1/1027
摘要： According to an embodiment, a semiconductor integrated circuit includes an amplifier, an interference wave suppression unit, a coupler and a filter control circuit. The interference wave suppression unit includes a filter being controlled to be on or off. The filter is configured to suppress an interference wave component of an amplified signal to output the signal as an output signal when the filter is on. The coupler is configured to detect an input signal or the output signal. The filter control circuit controls the filter to be on when a signal level of a detection input signal or a detection output signal detected by the coupler is greater than or equal to a reference value, and controls the filter to be off when the signal level is smaller than the reference value, at arbitrary determination timing in a period of time between a transmission and a reception.
摘要翻译：根据实施例，半导体集成电路包括放大器，干扰波抑制单元，耦合器和滤波器控制电路。干扰波抑制单元包括被控制为开或关的滤波器。滤波器被配置为当滤波器打开时抑制放大信号的干扰波分量作为输出信号输出信号。耦合器被配置为检测输入信号或输出信号。当检测输入信号或耦合器检测到的检测输出信号的信号电平大于或等于参考值时，滤波器控制电路控制滤波器导通，并且当信号电平为小于参考值，在发送和接收之间的时间段内的任意确定定时。

4. 发明授权

US08232839B2 Semiconductor integrated circuit device and transmission and reception system 失效
标题翻译：半导体集成电路器件和发射和接收系统
公开(公告)号：US08232839B2
公开(公告)日：2012-07-31
申请号：US12824079
申请日：2010-06-25
申请人： Mitsuyuki Ashida
发明人： Mitsuyuki Ashida
IPC分类号： H03F1/26
CPC分类号： H03F1/3241 , H03G3/3042
摘要： A semiconductor integrated circuit device comprising a linearizer that has a plurality of switchable first gain characteristics, the linearizer switching to the first gain characteristic to generate an intermediate signal from an input signal by using the switched first gain characteristic, and outputting the intermediate signal to a circuit having a second gain characteristic, wherein the linearizer includes: a linearization unit that has at least one of first rectifier, and linearizes the input signal; and a linearization reducing unit that has a plurality of second rectifiers having polarity opposite to polarity of the first rectifier and a first switching unit selecting at least one of the second rectifiers based on a control signal, the linearization reducing unit being connected in parallel to the linearization unit and reducing linearization of the input signal by the linearization unit.
摘要翻译：一种半导体集成电路器件，包括具有多个可切换的第一增益特性的线性化器，所述线性化器通过使用所述切换的第一增益特性切换到所述第一增益特性以产生来自输入信号的中间信号，并将所述中间信号输出到电路具有第二增益特性，其中所述线性化器包括：线性化单元，其具有第一整流器中的至少一个，并且对输入信号进行线性化; 以及线性化减少单元，其具有极性与第一整流器的极性相反的多个第二整流器和第一开关单元，其基于控制信号选择第二整流器中的至少一个，所述线性化降低单元与线性化单元，并且通过线性化单元减少输入信号的线性化。

5. 发明申请

US20110210788A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TRANSMISSION AND RECEPTION SYSTEM 失效
标题翻译：半导体集成电路设备和传输和接收系统
公开(公告)号：US20110210788A1
公开(公告)日：2011-09-01
申请号：US12824079
申请日：2010-06-25
申请人： Mitsuyuki Ashida
发明人： Mitsuyuki Ashida
IPC分类号： H03F1/26
CPC分类号： H03F1/3241 , H03G3/3042
摘要： A semiconductor integrated circuit device comprising a linearizer that has a plurality of switchable first gain characteristics, the linearizer switching to the first gain characteristic to generate an intermediate signal from an input signal by using the switched first gain characteristic, and outputting the intermediate signal to a circuit having a second gain characteristic, wherein the linearizer includes: a linearization unit that has at least one of first rectifier, and linearizes the input signal; and a linearization reducing unit that has a plurality of second rectifiers having polarity opposite to polarity of the first rectifier and a first switching unit selecting at least one of the second rectifiers based on a control signal, the linearization reducing unit being connected in parallel to the linearization unit and reducing linearization of the input signal by the linearization unit.
摘要翻译：一种半导体集成电路器件，包括具有多个可切换的第一增益特性的线性化器，所述线性化器通过使用所述切换的第一增益特性切换到所述第一增益特性以产生来自输入信号的中间信号，并将所述中间信号输出到电路具有第二增益特性，其中所述线性化器包括：线性化单元，其具有第一整流器中的至少一个，并且对输入信号进行线性化; 以及线性化减少单元，其具有极性与第一整流器的极性相反的多个第二整流器和第一开关单元，其基于控制信号选择第二整流器中的至少一个，所述线性化降低单元与线性化单元，并且通过线性化单元减少输入信号的线性化。

6. 发明申请

US20110063050A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20110063050A1
公开(公告)日：2011-03-17
申请号：US12881446
申请日：2010-09-14
申请人： Mitsuyuki Ashida
发明人： Mitsuyuki Ashida
IPC分类号： H03H7/01
CPC分类号： H03H7/09 , H03F3/45179
摘要： Embodiments described a semiconductor integrated circuit includes: a first coil and a second coil which have a mutual coupling and are connected in parallel to each other; a third coil connected in series to the first coil and the second coil; a first capacitor connected in parallel to the first coil; a second capacitor connected in parallel to the second coil; a first input terminal connected to an end of the first coil and an end of the first capacitor; a second input terminal connected to an end of the second coil and an end of the second capacitor; and an input-signal supplying portion configured to supply input signals of opposite phases to the first input terminal and the second input terminal, respectively.
摘要翻译：所描述的实施例的半导体集成电路包括：第一线圈和第二线圈，其具有互耦并且彼此并联连接; 与第一线圈和第二线圈串联连接的第三线圈; 与第一线圈并联连接的第一电容器; 与第二线圈并联连接的第二电容器; 连接到第一线圈的端部和第一电容器的端部的第一输入端子; 连接到第二线圈的端部和第二电容器的端部的第二输入端子; 以及输入信号提供部分，被配置为分别向第一输入端子和第二输入端子提供相反相位的输入信号。

7. 发明授权

US08654909B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US08654909B2
公开(公告)日：2014-02-18
申请号：US13237050
申请日：2011-09-20
申请人： Mitsuyuki Ashida , Hideaki Majima
发明人： Mitsuyuki Ashida , Hideaki Majima
IPC分类号： H03D1/04 , H03D1/06 , H03K5/01 , H03K6/04 , H04B1/10 , H04L1/00 , H04L25/08
CPC分类号： H04B1/1027
摘要： According to an embodiment, a semiconductor integrated circuit includes an amplifier, an interference wave suppression unit, a coupler and a filter control circuit. The interference wave suppression unit includes a filter being controlled to be on or off. The filter is configured to suppress an interference wave component of an amplified signal to output the signal as an output signal when the filter is on. The coupler is configured to detect an input signal or the output signal. The filter control circuit controls the filter to be on when a signal level of a detection input signal or a detection output signal detected by the coupler is greater than or equal to a reference value, and controls the filter to be off when the signal level is smaller than the reference value, at arbitrary determination timing in a period of time between a transmission and a reception.
摘要翻译：根据实施例，半导体集成电路包括放大器，干扰波抑制单元，耦合器和滤波器控制电路。干扰波抑制单元包括被控制为开或关的滤波器。滤波器被配置为当滤波器打开时抑制放大信号的干扰波分量作为输出信号输出信号。耦合器被配置为检测输入信号或输出信号。当检测输入信号或耦合器检测到的检测输出信号的信号电平大于或等于参考值时，滤波器控制电路控制滤波器导通，并且当信号电平为小于参考值，在发送和接收之间的时间段内的任意确定定时。

8. 发明授权

US07675355B2 Semiconductor device that degrades leak current of a transistor 失效
标题翻译：降低晶体管漏电流的半导体器件
公开(公告)号：US07675355B2
公开(公告)日：2010-03-09
申请号：US11758394
申请日：2007-06-05
申请人： Mitsuyuki Ashida , Mototsugu Hamada
发明人： Mitsuyuki Ashida , Mototsugu Hamada
IPC分类号： H03M1/12
CPC分类号： H03K19/0013
摘要： A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.
摘要翻译：半导体器件具有作为第一导电型MOS晶体管的主晶体管，并且漏极连接到第一电位; 连接在所述主晶体管的源极和第二电位之间的第一开关电路; 作为第一导电型MOS晶体管的虚设晶体管，其源极也用作所述主晶体管的源极; 以及连接在所述虚拟晶体管的漏极与所述第一电位或所述第二电位之间的第二开关电路。

9. 发明申请

US20100117161A1 SEMICONDUCTOR DEVICE THAT DEGRADES LEAK CURRENT OF A TRANSISTOR 有权
标题翻译：降低晶体管漏电流的半导体器件
公开(公告)号：US20100117161A1
公开(公告)日：2010-05-13
申请号：US12692387
申请日：2010-01-22
申请人： Mitsuyuki ASHIDA , Mototsugu Hamada
发明人： Mitsuyuki ASHIDA , Mototsugu Hamada
IPC分类号： H01L29/66
CPC分类号： H03K19/0013
摘要： A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.
摘要翻译：半导体器件具有作为第一导电型MOS晶体管的主晶体管，并且漏极连接到第一电位; 连接在所述主晶体管的源极和第二电位之间的第一开关电路; 作为第一导电型MOS晶体管的虚设晶体管，其源极也用作所述主晶体管的源极; 以及连接在所述虚拟晶体管的漏极与所述第一电位或所述第二电位之间的第二开关电路。

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