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1. 发明申请

US20080080231A1 NONVOLATILE LATCH CIRCUIT AND NONVOLATILE FLIP-FLOP CIRCUIT 有权
标题翻译：非易失性电路和非易失性FLIP-FLOP电路
公开(公告)号：US20080080231A1
公开(公告)日：2008-04-03
申请号：US11848864
申请日：2007-08-31
申请人： Keiko Abe , Takahiro Hirai , Shiho Nakamura , Hirofumi Morise , Mototsugu Hamada
发明人： Keiko Abe , Takahiro Hirai , Shiho Nakamura , Hirofumi Morise , Mototsugu Hamada
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C14/0081
摘要： A nonvolatile latch circuit includes: a first gate part controlling to load or intercept an input signal based on a gate signal; a first logic gate functioning as an inverter or a gate outputting a constant voltage in response to the first control signal; a second logic gate functioning as an inverter or a gate outputting the constant voltage in response to the first control signal; a second gate part controlling to load or intercept the output of the second logic gate based on an inverted signal of the gate signal and sends the output of the second logic gate to an first input terminal of the first logic gate; and first and second injection type MTJ elements provided between the driving power supply and the first and second logic gates and changing in resistance depending upon a current flow direction.
摘要翻译：非易失性锁存电路包括：第一栅极部分，其基于栅极信号控制输入信号的加载或截取; 用作反相器的第一逻辑门或响应于第一控制信号输出恒定电压的栅极; 用作反相器的第二逻辑门或响应于第一控制信号输出恒定电压的栅极; 第二栅极部分，用于基于所述栅极信号的反相信号来加载或截取所述第二逻辑门的输出，并将所述第二逻辑门的输出发送到所述第一逻辑门的第一输入端; 以及设置在驱动电源和第一和第二逻辑门之间的第一和第二注入型MTJ元件，并根据电流流动方向改变电阻。

2. 发明授权

US07733145B2 Nonvolatile latch circuit and nonvolatile flip-flop circuit 有权
标题翻译：非易失性锁存电路和非易失性触发器电路
公开(公告)号：US07733145B2
公开(公告)日：2010-06-08
申请号：US11848864
申请日：2007-08-31
申请人： Keiko Abe , Takahiro Hirai , Shiho Nakamura , Hirofumi Morise , Mototsugu Hamada
发明人： Keiko Abe , Takahiro Hirai , Shiho Nakamura , Hirofumi Morise , Mototsugu Hamada
IPC分类号： H03K3/00 , H03K3/45
CPC分类号： G11C11/16 , G11C14/0081
摘要： A nonvolatile latch circuit includes: a first gate part controlling to load or intercept an input signal based on a gate signal; a first logic gate functioning as an inverter or a gate outputting a constant voltage in response to the first control signal; a second logic gate functioning as an inverter or a gate outputting the constant voltage in response to the first control signal; a second gate part controlling to load or intercept the output of the second logic gate based on an inverted signal of the gate signal and sends the output of the second logic gate to an first input terminal of the first logic gate; and first and second injection type MTJ elements provided between the driving power supply and the first and second logic gates and changing in resistance depending upon a current flow direction.
摘要翻译：非易失性锁存电路包括：第一栅极部分，其基于栅极信号控制输入信号的加载或截取; 用作反相器的第一逻辑门或响应于第一控制信号输出恒定电压的栅极; 用作反相器的第二逻辑门或响应于第一控制信号输出恒定电压的栅极; 第二栅极部分，用于基于所述栅极信号的反相信号来加载或截取所述第二逻辑门的输出，并将所述第二逻辑门的输出发送到所述第一逻辑门的第一输入端; 以及设置在驱动电源和第一和第二逻辑门之间的第一和第二注入型MTJ元件，并根据电流流动方向改变电阻。

3. 发明授权

US07606096B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07606096B2
公开(公告)日：2009-10-20
申请号：US11872264
申请日：2007-10-15
申请人： Mototsugu Hamada , TakahirO Hirai , Shiho Nakamura , Hirofumi Morise , Keiko Abe
发明人： Mototsugu Hamada , TakahirO Hirai , Shiho Nakamura , Hirofumi Morise , Keiko Abe
IPC分类号： G11C7/00 , G11C11/00 , H03K3/02
CPC分类号： G11C13/00 , G11C5/14 , G11C13/004 , G11C13/0069 , G11C14/009 , G11C2013/0042 , G11C2013/0054 , G11C2013/0073
摘要： A semiconductor integrated circuit device, has a first variable resistor element and a second variable resistor element whose resistances are changed complementarily depending on a current; and a current path switching circuit that supplies said current from a power supply by switching between current paths according to whether a normal operation mode or a read mode is input externally, wherein said power supply is turned off and then turned on again in said normal operation mode, and in this state, data corresponding to the relationship between the magnitudes of the resistances of said first variable resistor element and said second variable resistor element is read in said read mode.
摘要翻译：半导体集成电路器件具有第一可变电阻器元件和第二可变电阻器元件，其电阻根据电流互补地改变; 以及电流路径切换电路，其通过根据正常操作模式还是读取模式在电流路径之间切换来从电源提供所述电流，其中所述电源在所述正常操作中被关闭然后再次导通模式，并且在该状态下，在所述读取模式中读取与所述第一可变电阻元件和所述第二可变电阻元件的电阻的大小之间的关系对应的数据。

4. 发明申请

US20080298117A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20080298117A1
公开(公告)日：2008-12-04
申请号：US11872264
申请日：2007-10-15
申请人： Mototsugu Hamada , Takahiro Hirai , Shiho Nakamura , Hirofumi Morise , Keiko Abe
发明人： Mototsugu Hamada , Takahiro Hirai , Shiho Nakamura , Hirofumi Morise , Keiko Abe
IPC分类号： G11C11/34
CPC分类号： G11C13/00 , G11C5/14 , G11C13/004 , G11C13/0069 , G11C14/009 , G11C2013/0042 , G11C2013/0054 , G11C2013/0073
摘要： A semiconductor integrated circuit device, has a first variable resistor element and a second variable resistor element whose resistances are changed complementarily depending on a current; and a current path switching circuit that supplies said current from a power supply by switching between current paths according to whether a normal operation mode or a read mode is input externally, wherein said power supply is turned off and then turned on again in said normal operation mode, and in this state, data corresponding to the relationship between the magnitudes of the resistances of said first variable resistor element and said second variable resistor element is read in said read mode.
摘要翻译：半导体集成电路器件具有第一可变电阻器元件和第二可变电阻器元件，其电阻根据电流互补地改变; 以及电流路径切换电路，其通过根据正常操作模式还是读取模式在电流路径之间切换来从电源提供所述电流，其中所述电源在所述正常操作中被关闭然后再次导通模式，并且在该状态下，在所述读取模式中读取与所述第一可变电阻元件和所述第二可变电阻元件的电阻的大小之间的关系对应的数据。

5. 发明授权

US07397271B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07397271B2
公开(公告)日：2008-07-08
申请号：US11502572
申请日：2006-08-11
申请人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
发明人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17728 , H03K19/1778
摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal; a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state; and a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state.
摘要翻译：半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。所述逻辑单元中的至少一个具有：包括MIS晶体管的标准单元，所述标准单元包括输入来自前一级的输出信号的输入端作为输入信号和输出端，所述标准单元执行基于所述输入信号进行预定的逻辑运算，并输出所述逻辑运算的结果作为来自所述输出端子的输出信号; 设置在标准单元的输出端子与第一电源电压之间的第一导电型第一MIS晶体管，所述第一MIS晶体管包括输入电路控制信号的控制端子和提供电路控制信号的第一MIS晶体管基于电路控制信号向标准单元的输出端施加第一电源电压，以使标准单元进入操作停止状态; 以及设置在所述标准单元和第二电源电压之间的第二导电型第二MIS晶体管，所述第二MIS晶体管包括输入所述电路控制信号的控制端子，所述第二MIS晶体管切断漏电流的基于电路控制信号的标准单元中的MIS晶体管，以使标准单元进入操作停止状态。

6. 发明申请

US20070296485A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070296485A1
公开(公告)日：2007-12-27
申请号：US11758394
申请日：2007-06-05
申请人： Mitsuyuki ASHIDA , Mototsugu Hamada
发明人： Mitsuyuki ASHIDA , Mototsugu Hamada
IPC分类号： H03H11/40
CPC分类号： H03K19/0013
摘要： A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.
摘要翻译：半导体器件具有作为第一导电型MOS晶体管的主晶体管，并且漏极连接到第一电位; 连接在所述主晶体管的源极和第二电位之间的第一开关电路; 作为第一导电型MOS晶体管的虚设晶体管，其源极也用作所述主晶体管的源极; 以及连接在所述虚拟晶体管的漏极与所述第一电位或所述第二电位之间的第二开关电路。

7. 发明申请

US20070236253A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20070236253A1
公开(公告)日：2007-10-11
申请号：US11695771
申请日：2007-04-03
申请人： Fumihiko Tachibana , Mototsugu Hamada
发明人： Fumihiko Tachibana , Mototsugu Hamada
IPC分类号： H03K19/094
CPC分类号： H03K19/094 , H03K19/0013 , H03K19/0016
摘要： A semiconductor integrated circuit comprising: a logic section having a plurality of first transistors; a second transistor, having source and drain electrodes connected between a first reference voltage line and a first reference voltage line side terminal of the logic section, and having a gate electrode to which a control signal for controlling whether to supply a power source voltage to the logic section is inputted; a third transistor having a source and drain electrode connected between an output terminal of the logic section and a second reference voltage line, wherein the third transistor turns off when the second transistor turns on, and turns on when the second transistor turns off; and a control section, connected to a gate electrode of the third transistor, and performing on/off control of the third transistor.
摘要翻译：一种半导体集成电路，包括：具有多个第一晶体管的逻辑部分; 第二晶体管，其源极和漏极连接在逻辑部分的第一参考电压线和第一参考电压线侧端之间，并且具有栅电极，控制信号用于控制是否将电源电压提供给逻辑部分被输入; 第三晶体管，其源极和漏极连接在逻辑部分的输出端和第二参考电压线之间，其中当第二晶体管导通时，第三晶体管截止，当第二晶体管截止时，第三晶体管导通; 以及控制部分，连接到第三晶体管的栅电极，并且执行第三晶体管的导通/截止控制。

8. 发明授权

US07551019B2 Semiconductor integrated circuit and source voltage/substrate bias control circuit 失效
标题翻译：半导体集成电路和源极电压/衬底偏置控制电路
公开(公告)号：US07551019B2
公开(公告)日：2009-06-23
申请号：US11764605
申请日：2007-06-18
申请人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
发明人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G05F3/16 , H03L1/00
CPC分类号： G05F3/205
摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

9. 发明授权

US07479806B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07479806B2
公开(公告)日：2009-01-20
申请号：US11476106
申请日：2006-06-28
申请人： Chen Kong Teh , Mototsugu Hamada
发明人： Chen Kong Teh , Mototsugu Hamada
IPC分类号： H03K19/096 , H03K3/12
CPC分类号： H03K3/012 , H03K3/356139
摘要： The semiconductor integrated circuit device is a semiconductor integrated circuit device having a pulse generator and a latch circuit. The pulse generator has a first charge/discharge path and a second charge/discharge path and a charge unit for pre-charging first nodes. The first charge/discharge path and the second charge/discharge path include: two first switching units, connected to the first nodes, and configured to control, according to an input signal, conduction and non-conduction of the first charge/discharge path and the second charge/discharge path; and a second switching unit, disposed between a second node and a reference voltage node, and configured to be turned on in a period prior to capturing the input signal to allow an electric charge accumulated at the second node to be discharged to the reference voltage node, and at the same time, configured to be turned on in a period of capturing the input signal to allow the first node to discharge.
摘要翻译：半导体集成电路器件是具有脉冲发生器和锁存电路的半导体集成电路器件。脉冲发生器具有第一充电/放电路径和第二充电/放电路径以及用于对第一节点进行预充电的充电单元。第一充电/放电路径和第二充电/放电路径包括：两个第一开关单元，连接到第一节点，并且被配置为根据输入信号来控制第一充电/放电路径的导通和非导通，以及第二充电/放电路径; 以及第二开关单元，设置在第二节点和参考电压节点之间，并且被配置为在捕获输入信号之前的周期中导通，以允许在第二节点处累积的电荷被放电到参考电压节点并且同时被配置为在捕获输入信号的时段中导通以允许第一节点放电。

10. 发明授权

US07456669B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07456669B2
公开(公告)日：2008-11-25
申请号：US11439271
申请日：2006-05-24
申请人： Chen Kong Teh , Mototsugu Hamada
发明人： Chen Kong Teh , Mototsugu Hamada
IPC分类号： H03K3/00
CPC分类号： H03K3/012 , H03K3/037 , H03K17/04106 , H03K17/102
摘要： A semiconductor integrated circuit device includes a comparator for making a comparison between a logical value of an input signal and a logical value of an output signal and outputting a combination signal having a combination of the logical values; and a flip-flop circuit configured to maintain a state of the output signal with electric power for maintaining the state less than electric power for state transition of the output signal in the case where the combination of the logical values of the combination signal is a predetermined combination, and wherein the comparator outputs the combination signal having the predetermined combination to an input terminal portion in the case of determining that the input signal does not vary the state of the output signal based on a result of the comparison between the logical value of the input signal and the logical value of the output signal.
摘要翻译：半导体集成电路装置包括：比较器，用于比较输入信号的逻辑值和输出信号的逻辑值，并输出具有逻辑值组合的组合信号; 以及触发器电路，被配置为在组合信号的逻辑值的组合是预定的情况下，保持具有电力的输出信号的状态以保持小于输出信号的状态转换的电力的状态组合，并且其中在确定输入信号不改变输出信号的状态的情况下，比较器将输出具有预定组合的组合信号输出到输入端子部分，输入信号和输出信号的逻辑值。

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