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1. 发明申请

US20060198198A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060198198A1
公开(公告)日：2006-09-07
申请号：US11342617
申请日：2006-01-31
申请人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
发明人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C5/147
摘要： According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.
摘要翻译：根据本发明，提供了一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

2. 发明授权

US07417489B2 Semiconductor integrated circuit having controller controlling the change rate of power voltage 有权
标题翻译：具有控制器控制电源电压变化率的半导体集成电路
公开(公告)号：US07417489B2
公开(公告)日：2008-08-26
申请号：US11342617
申请日：2006-01-31
申请人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
发明人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
IPC分类号： G05F1/10
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.
摘要翻译：一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

3. 发明授权

US07487370B2 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US07487370B2
公开(公告)日：2009-02-03
申请号：US11216018
申请日：2005-09-01
申请人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
发明人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.
摘要翻译：根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平。电源电路基于施加到其上的第二控制信号输出具有第二电平的内部电源电压。

4. 发明申请

US20060271799A1 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US20060271799A1
公开(公告)日：2006-11-30
申请号：US11216018
申请日：2005-09-01
申请人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
发明人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： According to the present invention, there is provided a semiconductor device comprising: a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level, wherein said power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.
摘要翻译：根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平，其中所述电源电路基于施加到其的第二控制信号输出具有第二电平的内部电源电压。

5. 发明授权

US07551019B2 Semiconductor integrated circuit and source voltage/substrate bias control circuit 失效
标题翻译：半导体集成电路和源极电压/衬底偏置控制电路
公开(公告)号：US07551019B2
公开(公告)日：2009-06-23
申请号：US11764605
申请日：2007-06-18
申请人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
发明人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G05F3/16 , H03L1/00
CPC分类号： G05F3/205
摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

6. 发明申请

US20050093611A1 Semiconductor integrated circuit and source voltage/substrate bias control circuit 有权
标题翻译：半导体集成电路和源极电压/衬底偏置控制电路
公开(公告)号：US20050093611A1
公开(公告)日：2005-05-05
申请号：US10899004
申请日：2004-07-27
申请人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
发明人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： H01L27/04 , G05F3/20 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K3/01 , H03K17/00
CPC分类号： G05F3/205
摘要： A semiconductor integrated circuit comprises a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generating circuit applying substrate biases to individual said well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：半导体集成电路包括半导体衬底; 多个阱区，形成在所述半导体衬底的一个表面上并彼此电隔离; 形成在所述阱区中的多个MOS晶体管; 以及衬底偏置产生电路，其基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差将单独的所述阱区域施加衬底偏置，以使各MOS晶体管的阈值电压与正常阈值电压一致。

7. 发明授权

US06252452B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06252452B1
公开(公告)日：2001-06-26
申请号：US09382010
申请日：1999-08-24
申请人： Fumitoshi Hatori , Tetsuya Fujita
发明人： Fumitoshi Hatori , Tetsuya Fujita
IPC分类号： G05F110
CPC分类号： H03K3/0315 , G05F3/205 , H03K17/223 , H03K19/00315
摘要： In a semiconductor device operating upon receiving two power supply potentials (VDD1, VDD2) (VDD1
摘要翻译：在接收到两个电源电位（VDD1，VDD2）（VDD1

8. 发明授权

US07586364B2 Power supply voltage controlling circuit and semiconductor integrated circuit 失效
标题翻译：电源电压控制电路和半导体集成电路
公开(公告)号：US07586364B2
公开(公告)日：2009-09-08
申请号：US11758343
申请日：2007-06-05
申请人： Tetsuya Fujita , Mototsugu Hamada
发明人： Tetsuya Fujita , Mototsugu Hamada
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： A power supply voltage controlling circuit has a voltage regulator circuit that supplies a current to an output terminal from at least any of a first power supply and a second power supply, and compares an output voltage at the output terminal with a first reference voltage to adjust the output voltage to approach the first reference voltage; and a controller circuit that supplies the first reference voltage to the voltage regulator circuit and controls the voltage regulator circuit by outputting, to the voltage regulator circuit, at least any of a first enable signal for enabling the first power supply to supply a current to the output terminal and a second enable signal for enabling the second power supply to supply a current to the output terminal.
摘要翻译：电源电压控制电路具有电压调节器电路，其从第一电源和第二电源中的至少任一个向输出端提供电流，并且将输出端子处的输出电压与第一参考电压进行比较以进行调整输出电压接近第一参考电压; 以及控制器电路，其将所述第一参考电压提供给所述电压调节器电路，并且通过向所述稳压器电路输出至少任一第一使能信号来控制所述稳压器电路，以使所述第一电源能够向所述电压调节器电路提供电流输出端子和第二使能信号，用于使第二电源能够向输出端子提供电流。

9. 发明授权

US07245177B2 Semiconductor integrated circuit and source voltage/substrate bias control circuit 有权
标题翻译：半导体集成电路和源极电压/衬底偏置控制电路
公开(公告)号：US07245177B2
公开(公告)日：2007-07-17
申请号：US10899004
申请日：2004-07-27
申请人： Tetsuya Fujita , Motosugu Hamada , Hiroyuki Hara
发明人： Tetsuya Fujita , Motosugu Hamada , Hiroyuki Hara
IPC分类号： G05F3/24
CPC分类号： G05F3/205
摘要： This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：本公开涉及半导体集成电路包括半导体衬底; 多个阱区，形成在所述半导体衬底的一个表面上并彼此电隔离; 形成在所述阱区中的多个MOS晶体管; 以及衬底偏置发生器，其基于实际测量的阈值电压下的MOS晶体管的工艺导出方差，将衬底偏压到各个阱区域，以使各个MOS晶体管的阈值电压与正常阈值电压一致。

10. 发明授权

US08464517B2 Method of controlling NOx purification system, and NOx purification system 有权
标题翻译：控制NOx净化系统和NOx净化系统的方法
公开(公告)号：US08464517B2
公开(公告)日：2013-06-18
申请号：US12736090
申请日：2008-11-27
申请人： Tetsuya Fujita
发明人： Tetsuya Fujita
IPC分类号： F01N3/00 , F01N3/10
CPC分类号： B01D53/9431 , B01D53/9495 , B01D2251/2062 , B01D2257/404 , F01N3/0814 , F01N3/103 , F01N3/106 , F01N3/2053 , F01N3/2066 , F01N3/208 , F01N13/009 , F01N2410/00 , F01N2410/12 , F01N2560/026 , F01N2610/02 , Y02A50/2345 , Y02T10/24
摘要： Method to reduce NOx contained in an exhaust gas by including an oxidation catalyst device and a selective reduction type NOx catalyst device, which are arranged in this order from an upstream side, and a NOx purification system. Whether a volume of NO2 adsorbed in the oxidation catalyst device increases or decreases is estimated, and a flow rate of exhaust gas which bypasses the oxidation catalyst device on a basis of the increase or decrease in the estimated volume of adsorbed NO2 is controlled. This avoids incorrect supply of ammonia.
摘要翻译：通过包括从上游侧依次配置的氧化催化剂装置和选择还原型NOx催化剂装置来还原废气中所含的NOx的方法和NOx净化系统。估计在氧化催化剂装置中吸附的NO 2的体积是否增加，并且控制基于吸附的NO 2的估计体积的增加或减少而绕过氧化催化剂装置的废气的流量。这样可以避免氨的供应不正确。

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