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1. 发明授权

US08386881B2 Semiconductor memory device and method of controlling the same 有权
公开(公告)号：US08386881B2
公开(公告)日：2013-02-26
申请号：US13465624
申请日：2012-05-07
申请人： Shinichi Kanno , Hironori Uchikawa
发明人： Shinichi Kanno , Hironori Uchikawa
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

2. 发明申请

US20110197110A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
公开(公告)号：US20110197110A1
公开(公告)日：2011-08-11
申请号：US13090539
申请日：2011-04-20
申请人： Shinichi KANNO , Hironori Uchikawa
发明人： Shinichi KANNO , Hironori Uchikawa
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

3. 发明申请

US20090183052A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20090183052A1
公开(公告)日：2009-07-16
申请号：US12404861
申请日：2009-03-16
申请人： Shinichi KANNO , Hironori Uchikawa
发明人： Shinichi KANNO , Hironori Uchikawa
IPC分类号： H03M13/05 , G06F11/22 , G06F11/07
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

4. 发明授权

US08069394B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08069394B2
公开(公告)日：2011-11-29
申请号：US13090499
申请日：2011-04-20
申请人： Shinichi Kanno , Hironori Uchikawa
发明人： Shinichi Kanno , Hironori Uchikawa
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

5. 发明授权

US08196008B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08196008B2
公开(公告)日：2012-06-05
申请号：US13090539
申请日：2011-04-20
申请人： Shinichi Kanno , Hironori Uchikawa
发明人： Shinichi Kanno , Hironori Uchikawa
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

6. 发明授权

US08117517B2 Semiconductor memory device and method of controlling the same 有权
公开(公告)号：US08117517B2
公开(公告)日：2012-02-14
申请号：US12404861
申请日：2009-03-16
申请人： Shinichi Kanno , Hironori Uchikawa
发明人： Shinichi Kanno , Hironori Uchikawa
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

7. 发明申请

US20110197109A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110197109A1
公开(公告)日：2011-08-11
申请号：US13090499
申请日：2011-04-20
申请人： Shinichi KANNO , Hironori Uchikawa
发明人： Shinichi KANNO , Hironori Uchikawa
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

8. 发明授权

US08751895B2 Semiconductor memory device and decoding method 有权
标题翻译：半导体存储器件及解码方法
公开(公告)号：US08751895B2
公开(公告)日：2014-06-10
申请号：US13569492
申请日：2012-08-08
申请人： Haruka Obata , Tatsuyuki Ishikawa , Hironori Uchikawa , Kenji Sakurada
发明人： Haruka Obata , Tatsuyuki Ishikawa , Hironori Uchikawa , Kenji Sakurada
IPC分类号： H03M13/00
CPC分类号： H03M13/112 , H03M13/1128 , H03M13/6583
摘要： A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.”
摘要翻译：半导体存储器件包括存储LDPC编码数据的半导体存储器单元和对编码数据进行解码的解码单元，其中，当绝对值为0时，解码单元使用后验似然比原理进行串行译码，的后验似率比不小于阈值，并且当列元素似然比的绝对值不小于阈值时，使用列元素似然比作为后验似然比，并且如果解码不成功即使在执行了预定的第一循环计数的迭代处理之后，或者如果校正子错误的数量变得小于预定的第一校正子错误计数，则解码单元收缩至少一些后验似然比的绝对值并且重置所有先验似然比到“0”

9. 发明授权

US08572465B2 Nonvolatile semiconductor memory system having first and second error correction units 有权
标题翻译：具有第一和第二误差校正单元的非易失性半导体存储器系统
公开(公告)号：US08572465B2
公开(公告)日：2013-10-29
申请号：US12848476
申请日：2010-08-02
申请人： Hironori Uchikawa , Yoshihisa Kondo
发明人： Hironori Uchikawa , Yoshihisa Kondo
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , H03M13/05 , Y02D10/13
摘要： A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.
摘要翻译：非易失性半导体存储器系统包括半导体存储器，至少一个第一纠错单元和至少一个第二纠错单元。半导体存储器存储用LDPC码编码的数据帧。所述至少一个第一纠错单元根据第一迭代解码算法对所述数据帧执行第一纠错。所述至少一个第二纠错单元对由所述至少一个第一误差校正单元校正错误的数据帧执行第二纠错。所述至少一个第二纠错单元根据使用具有比第一迭代解码算法的量化位数更多的量化消息的消息的第二迭代解码算法执行第二纠错。

10. 发明授权

US08332726B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08332726B2
公开(公告)日：2012-12-11
申请号：US13310003
申请日：2011-12-02
申请人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
发明人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储信息的多个存储单元。似然度计算器具有多个似然计算算法，用于从从存储单元读出的阈值中导出关于存储的数据位的似然值。错误校正单元通过使用在似然度计算器获得的似然值的迭代处理执行纠错。似然度计算器控制器根据从误差校正单元获得的迭代处理中的迭代次数的一定值，在似然度计算器中的似然计算算法中进行变化。

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