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1. 发明授权

US08572465B2 Nonvolatile semiconductor memory system having first and second error correction units 有权
标题翻译：具有第一和第二误差校正单元的非易失性半导体存储器系统
公开(公告)号：US08572465B2
公开(公告)日：2013-10-29
申请号：US12848476
申请日：2010-08-02
申请人： Hironori Uchikawa , Yoshihisa Kondo
发明人： Hironori Uchikawa , Yoshihisa Kondo
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , H03M13/05 , Y02D10/13
摘要： A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.
摘要翻译：非易失性半导体存储器系统包括半导体存储器，至少一个第一纠错单元和至少一个第二纠错单元。半导体存储器存储用LDPC码编码的数据帧。所述至少一个第一纠错单元根据第一迭代解码算法对所述数据帧执行第一纠错。所述至少一个第二纠错单元对由所述至少一个第一误差校正单元校正错误的数据帧执行第二纠错。所述至少一个第二纠错单元根据使用具有比第一迭代解码算法的量化位数更多的量化消息的消息的第二迭代解码算法执行第二纠错。

2. 发明申请

US20110219284A1 NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：非易失性半导体存储器系统
公开(公告)号：US20110219284A1
公开(公告)日：2011-09-08
申请号：US12848476
申请日：2010-08-02
申请人： Hironori Uchikawa , Yoshihisa Kondo
发明人： Hironori Uchikawa , Yoshihisa Kondo
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/10 , H03M13/05 , Y02D10/13
摘要： A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.
摘要翻译：非易失性半导体存储器系统包括半导体存储器，至少一个第一纠错单元和至少一个第二纠错单元。半导体存储器存储用LDPC码编码的数据帧。所述至少一个第一纠错单元根据第一迭代解码算法对所述数据帧执行第一纠错。所述至少一个第二纠错单元对由所述至少一个第一误差校正单元校正错误的数据帧执行第二纠错。所述至少一个第二纠错单元根据使用具有比第一迭代解码算法的量化位数更多的量化消息的消息的第二迭代解码算法执行第二纠错。

3. 发明授权

US08751895B2 Semiconductor memory device and decoding method 有权
标题翻译：半导体存储器件及解码方法
公开(公告)号：US08751895B2
公开(公告)日：2014-06-10
申请号：US13569492
申请日：2012-08-08
申请人： Haruka Obata , Tatsuyuki Ishikawa , Hironori Uchikawa , Kenji Sakurada
发明人： Haruka Obata , Tatsuyuki Ishikawa , Hironori Uchikawa , Kenji Sakurada
IPC分类号： H03M13/00
CPC分类号： H03M13/112 , H03M13/1128 , H03M13/6583
摘要： A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.”
摘要翻译：半导体存储器件包括存储LDPC编码数据的半导体存储器单元和对编码数据进行解码的解码单元，其中，当绝对值为0时，解码单元使用后验似然比原理进行串行译码，的后验似率比不小于阈值，并且当列元素似然比的绝对值不小于阈值时，使用列元素似然比作为后验似然比，并且如果解码不成功即使在执行了预定的第一循环计数的迭代处理之后，或者如果校正子错误的数量变得小于预定的第一校正子错误计数，则解码单元收缩至少一些后验似然比的绝对值并且重置所有先验似然比到“0”

4. 发明授权

US08332726B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08332726B2
公开(公告)日：2012-12-11
申请号：US13310003
申请日：2011-12-02
申请人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
发明人： Hironori Uchikawa , Tatsuyuki Ishikawa , Mitsuaki Honma
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储信息的多个存储单元。似然度计算器具有多个似然计算算法，用于从从存储单元读出的阈值中导出关于存储的数据位的似然值。错误校正单元通过使用在似然度计算器获得的似然值的迭代处理执行纠错。似然度计算器控制器根据从误差校正单元获得的迭代处理中的迭代次数的一定值，在似然度计算器中的似然计算算法中进行变化。

5. 发明授权

US08149623B2 Controller and non-volatile semiconductor memory device 有权
标题翻译：控制器和非易失性半导体存储器件
公开(公告)号：US08149623B2
公开(公告)日：2012-04-03
申请号：US12715772
申请日：2010-03-02
申请人： Hironori Uchikawa , Kenji Sakurada
发明人： Hironori Uchikawa , Kenji Sakurada
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/34
摘要： A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels, an estimation unit configured to estimate statistical parameter of a distribution of the second threshold voltage levels with respect to a first threshold voltage level according to writing data, based on the histogram, and a determination unit configured to determine a fifth threshold voltage level defining a boundary of a fourth threshold voltage level indicating a read result of the memory cells from the third threshold voltage levels based on the statistical parameter in such a manner that mutual information amount between the first threshold voltage level and the fourth threshold voltage level becomes maximum.
摘要翻译：控制器包括：生成单元，被配置为将存储单元中保持的第二阈值电压电平与预定的第三阈值电压电平之间的比较结果进行聚合，并生成第二阈值电压电平的直方图;估计单元，被配置为估计分布的统计参数基于所述直方图，根据写入数据相对于第一阈值电压电平的第二阈值电压电平，以及确定单元，被配置为确定第五阈值电压电平，所述第五阈值电压电平定义指示读取结果的第四阈值电压电平的边界基于所述统计参数从所述第三阈值电压电平的所述存储器单元，使得所述第一阈值电压电平和所述第四阈值电压电平之间的相互信息量变为最大。

6. 发明授权

US07639753B2 Receiving apparatus and demodulating method 失效
标题翻译：接收装置和解调方法
公开(公告)号：US07639753B2
公开(公告)日：2009-12-29
申请号：US11385835
申请日：2006-03-22
申请人： Hironori Uchikawa , Kohsuke Harada
发明人： Hironori Uchikawa , Kohsuke Harada
IPC分类号： H04B7/02
CPC分类号： H04L1/005 , H04L1/0057
摘要： Receiving-apparatus employed in MIMO-system includes space-filtering-unit configured to separate receive-signals to signal of first-data-sequence and signal of second-data-sequence on basis of estimation result, provisional-decoding-unit configured to LDPC-decode signal of first-data-sequence and signal of second-data-sequence with check-matrices which is modified in different-forms by fundamental-row-operation from each other, to obtain provisional-likelihood-ratio for first-data-sequence and second-data-sequence, provisional-output-unit configured to output provisional-first-data-sequence and provisional-second-data-sequence on the basis of provisional-likelihood-ratio for first-data-sequence and second-data-sequence respectively, replica-signal-generation-unit configured to generate replica-signal, on basis of provisional-first-data-sequence and provisional-second-data-sequence and estimation-result of propagation-path-estimation-unit, soft-decision-outputting-unit configured to obtain receive-likelihood-values of first-data-sequence and second-data-sequence, on basis of residual-signal obtained by subtracting replica-signal from receive-signals, actual-decoding-unit configured to LDPC-decode receive-likelihood-values, by using the check-matrices, to obtain likelihood-ratio of first-data-sequence and likelihood-ratio of second-data-sequence, and actual-output-unit configured to obtain first-data-sequence and second-data-sequence on the basis of likelihood-ratio of first-data-sequence generated by the actual-decoding-unit and likelihood-ratio of second-data-sequence to hard-decision.
摘要翻译：在MIMO系统中采用的接收装置包括空间滤波单元，其被配置为基于估计结果将接收信号分离为第一数据序列的信号和第二数据序列的信号，临时解码单元被配置为LDPC - 第一数据序列的解码信号和具有通过基本行操作以不同形式修改的校验矩阵的第二数据序列的信号，以获得第一数据序列的第一数据序列的临时似然比，序列和第二数据序列临时输出单元，被配置为基于第一数据序列和第二数据的临时似然比输出临时第一数据序列和临时第二数据序列分别基于临时第一数据序列和临时第二数据序列以及传播路径估计单元的估计结果，配置为生成副本信号的复制信号生成单元，软 - 确定输出单元配置为obt 基于通过从接收信号中减去副本信号而获得的残差信号，对第一数据序列和第二数据序列的接收似然值进行解码，实现解码单元被配置为LDPC解码接收似然值，通过使用校验矩阵来获得第一数据序列和第二数据序列的似然比的似然比以及被配置为获得第一数据序列和第二数据序列的实际输出单元的值，基于由实际解码单元生成的第一数据序列的似然比和第二数据序列的似然比与硬判决的顺序。

7. 发明申请

US20080005641A1 Apparatus, method and program for decoding 失效
标题翻译：用于解码的装置，方法和程序
公开(公告)号：US20080005641A1
公开(公告)日：2008-01-03
申请号：US11723336
申请日：2007-03-19
申请人： Hironori Uchikawa , Kohsuke Harada
发明人： Hironori Uchikawa , Kohsuke Harada
IPC分类号： H03M13/00
CPC分类号： H03M13/114 , H03M13/616 , H03M13/6362
摘要： A decoder is configured to include an acquisition-unit configured to acquire first respective likelihoods of data-bits and second respective likelihoods of parity-bits, the data-bits and the parity-bits included in code data obtained by LDPC-encoding the data-bits with a low density parity check matrix, a detecting-unit configured to detect reliabilities of the first respective likelihoods and the second respective likelihoods, a forming-unit configured to form an update schedule representing an order of updating the first and second respective likelihoods in order of increasing reliability, in accordance with the reliabilities, an updating-unit configured to update the first and second respective likelihoods in the order represented by the update schedule, with the low density parity check matrix, a discriminating-unit configured to execute hard decision of the likelihoods updated by the updating-unit, and a checking-unit configured to execute parity check of a discrimination result of the discriminating-unit, to obtain the code data.
摘要翻译：解码器被配置为包括：获取单元，被配置为获取奇偶校验比特的第一各自的似然性和奇偶校验比特的第二相应似然性，数据比特和奇偶校验比特包括在通过LDPC编码获得的代码数据中，具有低密度奇偶校验矩阵的比特，检测单元，被配置为检测第一各个似然性和第二各自似然性的可靠性;形成单元，被配置为形成表示更新第一和第二各自可能性的顺序的更新计划，根据可靠性增加的顺序，更新单元被配置为利用低密度奇偶校验矩阵以由更新调度表示的顺序更新第一和第二各自的可能性;鉴别单元，被配置为执行硬判决由更新单元更新的可能性;以及检查单元，被配置为执行对判别结果o的奇偶校验 f鉴别单元，以获得代码数据。

8. 发明授权

US08386881B2 Semiconductor memory device and method of controlling the same 有权
公开(公告)号：US08386881B2
公开(公告)日：2013-02-26
申请号：US13465624
申请日：2012-05-07
申请人： Shinichi Kanno , Hironori Uchikawa
发明人： Shinichi Kanno , Hironori Uchikawa
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

9. 发明授权

US08385117B2 Semiconductor memory device and decoding method 有权
标题翻译：半导体存储器件及解码方法
公开(公告)号：US08385117B2
公开(公告)日：2013-02-26
申请号：US13233530
申请日：2011-09-15
申请人： Kenji Sakurada , Hironori Uchikawa
发明人： Kenji Sakurada , Hironori Uchikawa
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C8/08
摘要： A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select one required to read 1-bit data belonging to one of the pages to be read from among seven voltage sets which are composed of seven reference voltages for hard bit reading and a plurality of intermediate voltages for soft bit reading and perform control to apply the voltages of the selected voltage set as read voltages to the memory cell, a log likelihood ratio table storing section, and a decoder configured to decode read data using a log likelihood ratio.
摘要翻译：存储卡通过使用基于八个阈值电压分布的概率的迭代计算来解码存储在一个存储器单元中的三位数据，并且属于不同页面，每一页都是读取单元。存储卡包括字线控制部，被配置为从由七个用于硬比特读取的参考电压和多个中间值组成的七个电压组中选择要读取属于要读取的一个页面的1位数据所需的一个用于软位读取的电压，并且执行控制以将所设置的所选电压的电压设置为读取电压到存储器单元，对数似然比表存储部分和被配置为使用对数似然比来解码读取数据的解码器。

10. 发明授权

US08086932B2 Apparatus and method for decoding low-density parity check code 失效
标题翻译：用于解码低密度奇偶校验码的装置和方法
公开(公告)号：US08086932B2
公开(公告)日：2011-12-27
申请号：US12233673
申请日：2008-09-19
申请人： Hironori Uchikawa , Kohsuke Harada
发明人： Hironori Uchikawa , Kohsuke Harada
IPC分类号： H03M13/00
CPC分类号： H03M13/114 , H03M13/112 , H03M13/3738 , H03M13/658 , H03M13/6583
摘要： There is provided with a decoding apparatus for decoding a low-density parity check code defined by a parity check matrix, includes: a first operation unit configured to carry out a row operation for each row of the parity check matrix; a calculation unit configured to calculate a reliability coefficient with respect to establishment of a parity check equation defined by said each row, respectively; a second operation unit configured to carry out a column operation for said each row; and a controller configured to iteratively execute one set which includes respective processing by the first operation unit, the calculation unit and the second operation unit and omit the processing by the first operation unit and the calculation unit for a row for which the reliability coefficient has satisfied a threshold.
摘要翻译：提供了一种用于解码由奇偶校验矩阵定义的低密度奇偶校验码的解码装置，包括：第一操作单元，被配置为对奇偶校验矩阵的每一行执行行操作; 计算单元，被配置为分别计算关于由所述每行定义的奇偶校验方程的建立的可靠性系数; 第二操作单元，被配置为对所述每行执行列操作; 以及控制器，被配置为迭代地执行包括由所述第一操作单元，所述计算单元和所述第二操作单元进行的各自处理的一组，并且省略由所述第一操作单元和所述计算单元对于所述可靠性系数满足的行的处理一个门槛。

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