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1. 发明授权

US08751895B2 Semiconductor memory device and decoding method 有权
标题翻译：半导体存储器件及解码方法
公开(公告)号：US08751895B2
公开(公告)日：2014-06-10
申请号：US13569492
申请日：2012-08-08
申请人： Haruka Obata , Tatsuyuki Ishikawa , Hironori Uchikawa , Kenji Sakurada
发明人： Haruka Obata , Tatsuyuki Ishikawa , Hironori Uchikawa , Kenji Sakurada
IPC分类号： H03M13/00
CPC分类号： H03M13/112 , H03M13/1128 , H03M13/6583
摘要： A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.”
摘要翻译：半导体存储器件包括存储LDPC编码数据的半导体存储器单元和对编码数据进行解码的解码单元，其中，当绝对值为0时，解码单元使用后验似然比原理进行串行译码，的后验似率比不小于阈值，并且当列元素似然比的绝对值不小于阈值时，使用列元素似然比作为后验似然比，并且如果解码不成功即使在执行了预定的第一循环计数的迭代处理之后，或者如果校正子错误的数量变得小于预定的第一校正子错误计数，则解码单元收缩至少一些后验似然比的绝对值并且重置所有先验似然比到“0”

2. 发明授权

US08966351B2 Encoding apparatus, encoding method and semiconductor memory system 有权
标题翻译：编码装置，编码方法和半导体存储器系统
公开(公告)号：US08966351B2
公开(公告)日：2015-02-24
申请号：US13706663
申请日：2012-12-06
申请人： Hironori Uchikawa , Haruka Obata
发明人： Hironori Uchikawa , Haruka Obata
IPC分类号： H03M13/00 , H03M13/13 , H03M13/11
CPC分类号： H03M13/13 , H03M13/116 , H03M13/118 , H03M13/611
摘要： According to one embodiment, an encoding apparatus includes an input unit and a generation unit. The input unit inputs a data symbol sequence containing q(N−J) symbols (q, J, and N are integers, N>J). The generation unit generates a codeword containing qN symbols by adding a parity symbol sequence containing qJ symbols to the data symbol sequence. The codeword satisfies parity check equations of a parity check matrix of qJ rows×qN columns. A first submatrix of qJ rows×qJ columns that corresponds to the parity symbol sequence in the parity check matrix includes a second submatrix. The second submatrix includes a first identity matrix of qL rows×qL columns (L is an integer, J>L) and a first non-zero matrix of q(J−L) rows×qL columns.
摘要翻译：根据一个实施例，编码装置包括输入单元和生成单元。输入单元输入包含q（N-J）个符号（q，J和N是整数N> J）的数据符号序列。生成单元通过将包含qJ个符号的奇偶校验符号序列添加到数据符号序列来生成包含qN符号的码字。码字满足qJ行×qN列的奇偶校验矩阵的奇偶校验方程。对应于奇偶校验矩阵中的奇偶校验符号序列的qJ行×qJ列的第一子矩阵包括第二子矩阵。第二子矩阵包括qL行×qL列（L是整数J> L）和q（J-L）行×qL列的第一非零矩阵的第一单位矩阵。

3. 发明授权

US08645802B2 Error correction decoder and storage apparatus 失效
标题翻译：纠错解码器和存储装置
公开(公告)号：US08645802B2
公开(公告)日：2014-02-04
申请号：US13225759
申请日：2011-09-06
申请人： Haruka Obata , Hironori Uchikawa
发明人： Haruka Obata , Hironori Uchikawa
IPC分类号： H03M13/00
CPC分类号： H03M13/1142 , H03M13/1108 , H03M13/1111 , H03M13/451 , H03M13/458
摘要： According to embodiments, an error correction decoder carrying out iterative decoding for coded data based on LDPC code. The decoder comprises a generation unit and an inversion, control unit. The generation unit is configured to generate an inversion node list listing variable nodes connected to check nodes not satisfying a parity check when a code word cannot be obtained after carrying out the iterative decoding a first number of iterations. The inversion control unit is configured to choose a variable node which is a target for inversion from among the variable nodes listed in the inversion node list, and to carry out inversion processing which includes updating an input likelihood of the variable node which is the target for inversion temporarily by inverting a sign of an a posteriori likelihood of the variable node which is the target for inversion.
摘要翻译：根据实施例，纠错解码器基于LDPC码对编码数据进行迭代解码。解码器包括生成单元和反转控制单元。生成单元被配置为生成反转节点列表，其列出了在执行迭代解码第一迭代次数之后不能获得码字时，连接到校验节点不满足奇偶校验的变量节点。反转控制单元被配置为从反转节点列表中列出的可变节点中选择作为反转的目标的变量节点，并且执行包括更新作为目标的可变节点的输入似然性的反演处理通过反转作为反转目标的可变节点的后验似然度的符号来临时反转。

4. 发明申请

US20120226954A1 ERROR CORRECTION DECODER AND STORAGE APPARATUS 失效
标题翻译：错误修正解码器和存储设备
公开(公告)号：US20120226954A1
公开(公告)日：2012-09-06
申请号：US13225759
申请日：2011-09-06
申请人： Haruka Obata , Hironori Uchikawa
发明人： Haruka Obata , Hironori Uchikawa
IPC分类号： H03M13/11 , G06F11/10
CPC分类号： H03M13/1142 , H03M13/1108 , H03M13/1111 , H03M13/451 , H03M13/458
摘要： According to embodiments, an error correction decoder carrying out iterative decoding for coded data based on LDPC code. The decoder comprises a generation unit and an inversion, control unit. The generation unit is configured to generate an inversion node list listing variable nodes connected to check nodes not satisfying a parity check when a code word cannot be obtained after carrying out the iterative decoding a first number of iterations. The inversion control unit is configured to choose a variable node which is a target for inversion from among the variable nodes listed in the inversion node list, and to carry out inversion processing which includes updating an input likelihood of the variable node which is the target for inversion temporarily by inverting a sign of an a posteriori likelihood of the variable node which is the target for inversion.
摘要翻译：根据实施例，纠错解码器基于LDPC码对编码数据进行迭代解码。解码器包括生成单元和反转控制单元。生成单元被配置为生成反转节点列表，其列出了在执行迭代解码第一迭代次数之后不能获得码字时，连接到校验节点不满足奇偶校验的变量节点。反转控制单元被配置为从反转节点列表中列出的可变节点中选择作为反转的目标的变量节点，并且执行包括更新作为目标的可变节点的输入似然性的反演处理通过反转作为反转目标的可变节点的后验似然度的符号来临时反转。

5. 发明申请

US20110264983A1 SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND SIGNAL REPRODUCING APPARATUS 有权
标题翻译：信号处理装置，信号处理方法和信号再现装置
公开(公告)号：US20110264983A1
公开(公告)日：2011-10-27
申请号：US13088957
申请日：2011-04-18
申请人： Kenji Yoshida , Haruka Obata , Kohsuke Harada
发明人： Kenji Yoshida , Haruka Obata , Kohsuke Harada
IPC分类号： H03M13/41 , G06F11/10 , H03M13/29
CPC分类号： G11B20/10009 , G11B20/10055 , G11B20/10296 , G11B20/10509 , G11B2220/2516 , H03M13/2957 , H03M13/3905 , H03M13/4138 , H03M13/6306 , H03M13/6343
摘要： According to one embodiment, a signal processing device comprises a first waveform equalizer, a second waveform equalizer, a first Viterbi decoder, a second Viterbi decoder. The first and the second waveform equalizers equalize a waveform of the input signal according to first and second partial response characteristics and output first and second partial response signals. The first and second Viterbi decoders decode the first and the second partial response signals by means of Viterbi decoding process. The input signal is reproduced based on an output of the first Viterbi decoder and an output of the second Viterbi decoder.
摘要翻译：根据一个实施例，信号处理装置包括第一波形均衡器，第二波形均衡器，第一维特比解码器，第二维特比译码器。第一和第二波形均衡器根据第一和第二部分响应特性对输入信号的波形进行均衡，并输出第一和第二部分响应信号。第一和第二维特比解码器通过维特比解码处理解码第一和第二部分响应信号。基于第一维特比解码器的输出和第二维特比解码器的输出再现输入信号。

6. 发明授权

US08291304B2 Signal processing device, signal processing method, and signal reproducing apparatus 有权
标题翻译：信号处理装置，信号处理方法和信号再现装置
公开(公告)号：US08291304B2
公开(公告)日：2012-10-16
申请号：US13088957
申请日：2011-04-18
申请人： Kenji Yoshida , Haruka Obata , Kohsuke Harada
发明人： Kenji Yoshida , Haruka Obata , Kohsuke Harada
IPC分类号： H03M13/03
CPC分类号： G11B20/10009 , G11B20/10055 , G11B20/10296 , G11B20/10509 , G11B2220/2516 , H03M13/2957 , H03M13/3905 , H03M13/4138 , H03M13/6306 , H03M13/6343
摘要： According to one embodiment, a signal processing device comprises a first waveform equalizer, a second waveform equalizer, a first Viterbi decoder, a second Viterbi decoder. The first and the second waveform equalizers equalize a waveform of the input signal according to first and second partial response characteristics and output first and second partial response signals. The first and second Viterbi decoders decode the first and the second partial response signals by means of Viterbi decoding process. The input signal is reproduced based on an output of the first Viterbi decoder and an output of the second Viterbi decoder.
摘要翻译：根据一个实施例，信号处理装置包括第一波形均衡器，第二波形均衡器，第一维特比解码器，第二维特比译码器。第一和第二波形均衡器根据第一和第二部分响应特性对输入信号的波形进行均衡，并输出第一和第二部分响应信号。第一和第二维特比解码器通过维特比解码处理解码第一和第二部分响应信号。基于第一维特比解码器的输出和第二维特比解码器的输出再现输入信号。

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