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1. 发明申请

US20120043606A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120043606A1
公开(公告)日：2012-02-23
申请号：US13053452
申请日：2011-03-22
申请人： Shingo Sato , Hitoshi Shinohara , Keiko Kawamura
发明人： Shingo Sato , Hitoshi Shinohara , Keiko Kawamura
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7825 , H01L29/0623 , H01L29/063 , H01L29/0634 , H01L29/0886 , H01L29/4175 , H01L29/4236 , H01L29/66704 , H01L29/7393 , H01L29/782
摘要： According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a gate region, a gate insulating film, and an electric field relaxation region. The first semiconductor region includes a first portion and a second portion. The second semiconductor region includes a third portion and a fourth portion. The third semiconductor region includes a fifth portion and a sixth portion. The fourth semiconductor region is adjacent to the sixth portion. The gate region is provided inside a trench made in a second direction orthogonal to the first direction. The gate insulating film is provided between the gate region and an inner wall of the trench. The electric field relaxation region is provided between the third portion and the fifth portion and has an impurity concentration lower than an impurity concentration of the third semiconductor region.
摘要翻译：根据一个实施例，半导体器件包括第一半导体区域，第二半导体区域，第三半导体区域，第四半导体区域，栅极区域，栅极绝缘膜和电场弛豫区域。第一半导体区域包括第一部分和第二部分。第二半导体区域包括第三部分和第四部分。第三半导体区域包括第五部分和第六部分。第四半导体区域与第六部分相邻。栅极区域设置在与第一方向正交的第二方向上形成的沟槽内。栅极绝缘膜设置在栅极区域和沟槽的内壁之间。电场弛豫区设置在第三部分和第五部分之间，其杂质浓度低于第三半导体区域的杂质浓度。

2. 发明申请

US20120061747A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120061747A1
公开(公告)日：2012-03-15
申请号：US13052917
申请日：2011-03-21
申请人： Takeshi UCHIHARA , Yusuke Kawaguchi , Keiko Kawamura , Hitoshi Shinohara , Yosefu Fujiki
发明人： Takeshi UCHIHARA , Yusuke Kawaguchi , Keiko Kawamura , Hitoshi Shinohara , Yosefu Fujiki
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0626 , H01L29/0696 , H01L29/0886 , H01L29/1095 , H01L29/4238 , H01L29/66734 , H01L29/7808
摘要： According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a gate electrode in a trench shape, a contact region of the second conductivity type, a drain electrode, and a source electrode. The drift region is selectively provided in a drain layer of the first conductivity type from a surface of the drain layer to an inside of the drain layer. The base region is selectively provided in the drift region from a surface of the drift region to an inside of the drift region. The source region is selectively provided in the base region from a surface of the base region to an inside of the base region. The gate electrode penetrates from a part of the source region through the base region adjacent to the part of the source region to reach a part of the drift region in a direction substantially parallel to a major surface of the drain layer. The contact region is selectively provided on the surface of the drift region. The contact region contains an impurity having a concentration higher than an impurity concentration of the base region. The drain electrode is connected to the drain layer. The source electrode is connected to the source region and the contact region. The contact region extends from a side of the drain layer toward the drift region and does not contact the drain layer.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的漂移区域，第二导电类型的基极区域，第一导电类型的源极区域，沟槽形状的栅电极，第二导电类型的接触区域导电类型，漏电极和源电极。漂移区选择性地设置在从漏层的表面到漏层的内部的第一导电类型的漏极层中。基极区域选择性地设置在漂移区域中，从漂移区域的表面到漂移区域的内部。源极区域从基极区域的表面到基极区域的内部选择性地设置在基极区域中。栅极电极从源极区域的一部分穿过与源极区域相邻的基极区域，以在与漏极层的主表面基本平行的方向上到达漂移区域的一部分。接触区选择性地设置在漂移区的表面上。接触区域含有浓度高于碱性区域的杂质浓度的杂质。漏电极连接到漏极层。源电极连接到源极区域和接触区域。接触区域从漏极层的侧面朝向漂移区域延伸，并且不接触漏极层。

3. 发明申请

US20060160320A1 Method of fabricating a semiconductor device 失效
公开(公告)号：US20060160320A1
公开(公告)日：2006-07-20
申请号：US11299907
申请日：2005-12-13
申请人： Masanobu Tsuchitani , Hitoshi Shinohara , Keiko Kawamura
发明人： Masanobu Tsuchitani , Hitoshi Shinohara , Keiko Kawamura
IPC分类号： H01L21/76
CPC分类号： H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7811
摘要： A method of fabricating a semiconductor device includes: forming an insulating film on a semiconductor body to cover a termination area surrounding a cell area; forming a mask material film to cover the cell area and the insulating film; forming a resist film to cover the mask material film; patterning the resist film to have an opening serving as a gate-use resist pattern above the cell area and another opening serving as a dummy resist pattern above the insulating film; selectively etching the mask material film by use of the patterned resist film as a mask so that the insulating film is remained under the dummy resist pattern; selectively etching the semiconductor body by use of the patterned mask material film as another mask to form a trench in the cell area as corresponding to the gate-use resist pattern; and burying gate material in the trench to form the trench gate.

4. 发明授权

US07507630B2 Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07507630B2
公开(公告)日：2009-03-24
申请号：US11299907
申请日：2005-12-13
申请人： Masanobu Tsuchitani , Hitoshi Shinohara , Keiko Kawamura
发明人： Masanobu Tsuchitani , Hitoshi Shinohara , Keiko Kawamura
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7811
摘要： A method of fabricating a semiconductor device includes: forming an insulating film on a semiconductor body to cover a termination area surrounding a cell area; forming a mask material film to cover the cell area and the insulating film; forming a resist film to cover the mask material film; patterning the resist film to have an opening serving as a gate-use resist pattern above the cell area and another opening serving as a dummy resist pattern above the insulating film; selectively etching the mask material film by use of the patterned resist film as a mask so that the insulating film is remained under the dummy resist pattern; selectively etching the semiconductor body by use of the patterned mask material film as another mask to form a trench in the cell area as corresponding to the gate-use resist pattern; and burying gate material in the trench to form the trench gate.
摘要翻译：制造半导体器件的方法包括：在半导体本体上形成绝缘膜以覆盖围绕单元区域的端接区域; 形成掩模材料膜以覆盖单元区域和绝缘膜; 形成抗蚀剂膜以覆盖掩模材料膜; 将抗蚀剂膜图案化成在单元区域之上具有用作栅极用途抗蚀剂图案的开口，并且在绝缘膜上方具有用作模拟抗蚀剂图案的另一开口; 通过使用图案化的抗蚀剂膜作为掩模来选择性地蚀刻掩模材料膜，使得绝缘膜保持在假抗蚀剂图案下方; 通过使用图案化掩模材料膜作为另一掩模来选择性地蚀刻半导体本体，以在对应于栅极使用抗蚀剂图案的单元区域中形成沟槽; 并将栅极材料埋入沟槽中以形成沟槽栅极。

5. 发明授权

US08482060B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08482060B2
公开(公告)日：2013-07-09
申请号：US13052917
申请日：2011-03-21
申请人： Takeshi Uchihara , Yusuke Kawaguchi , Keiko Kawamura , Hitoshi Shinohara , Yosefu Fujiki
发明人： Takeshi Uchihara , Yusuke Kawaguchi , Keiko Kawamura , Hitoshi Shinohara , Yosefu Fujiki
IPC分类号： H01L29/772
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0626 , H01L29/0696 , H01L29/0886 , H01L29/1095 , H01L29/4238 , H01L29/66734 , H01L29/7808
摘要： According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a gate electrode in a trench shape, a contact region of the second conductivity type, a drain electrode, and a source electrode. The drift region is selectively provided in a drain layer of the first conductivity type from a surface of the drain layer to an inside of the drain layer. The base region is selectively provided in the drift region from a surface of the drift region to an inside of the drift region. The source region is selectively provided in the base region from a surface of the base region to an inside of the base region. The gate electrode penetrates from a part of the source region through the base region adjacent to the part of the source region to reach a part of the drift region in a direction substantially parallel to a major surface of the drain layer. The contact region is selectively provided on the surface of the drift region. The contact region contains an impurity having a concentration higher than an impurity concentration of the base region. The drain electrode is connected to the drain layer. The source electrode is connected to the source region and the contact region. The contact region extends from a side of the drain layer toward the drift region and does not contact the drain layer.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的漂移区域，第二导电类型的基极区域，第一导电类型的源极区域，沟槽形状的栅电极，第二导电类型的接触区域导电类型，漏电极和源电极。漂移区选择性地设置在第一导电类型的漏极层中，从漏极层的表面到漏极层的内部。基极区域选择性地设置在漂移区域中，从漂移区域的表面到漂移区域的内部。源极区域从基极区域的表面到基极区域的内部选择性地设置在基极区域中。栅极电极从源极区域的一部分穿过与源极区域相邻的基极区域，以在与漏极层的主表面基本平行的方向上到达漂移区域的一部分。接触区选择性地设置在漂移区的表面上。接触区域含有浓度高于碱性区域的杂质浓度的杂质。漏电极连接到漏极层。源电极连接到源极区域和接触区域。接触区域从漏极层的侧面朝向漂移区域延伸，并且不接触漏极层。

6. 发明申请

US20060292805A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060292805A1
公开(公告)日：2006-12-28
申请号：US11447114
申请日：2006-06-06
申请人： Keiko Kawamura , Shingo Sato
发明人： Keiko Kawamura , Shingo Sato
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/7802 , H01L29/165 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device is provided, which includes a first main electrode region having an upper main surface and a lower main surface; a drift layer of a first conductivity type formed on the upper main surface of the first main electrode region; a base layer of a second conductivity type formed on the drift layer; a second main electrode region of the first conductivity type formed on the base layer; a trench formed through the second main electrode region to the drift layer; a gate insulation film formed on an inner wall of the trench; and a gate electrode buried in the trench with the gate insulation film interposed therebetween, wherein the drift layer includes a graded region close to the first main electrode region, the graded region having band gap decreasing from the base layer toward the first main electrode region.
摘要翻译：提供一种半导体器件，其包括具有上主表面和下主表面的第一主电极区域; 形成在第一主电极区域的上主表面上的第一导电类型的漂移层; 形成在漂移层上的第二导电类型的基底层; 形成在基底层上的第一导电类型的第二主电极区域; 通过所述第二主电极区域形成到所述漂移层的沟槽; 形成在沟槽的内壁上的栅极绝缘膜; 以及埋设在所述沟槽中的栅电极，其间插入有所述栅极绝缘膜，其中所述漂移层包括靠近所述第一主电极区域的渐变区域，所述渐变区域具有从所述基极层朝向所述第一主电极区域的带隙。

7. 发明授权

US08183606B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08183606B2
公开(公告)日：2012-05-22
申请号：US12626414
申请日：2009-11-25
申请人： Ryuta Arai , Hidetoshi Asahara , Kouji Murakami , Keiko Kawamura
发明人： Ryuta Arai , Hidetoshi Asahara , Kouji Murakami , Keiko Kawamura
IPC分类号： H01L29/76
CPC分类号： H01L27/0255
摘要： A semiconductor device comprises an insulated gate field effect transistor and a protection diode. The insulated gate field effect transistor has a gate electrode formed on a gate insulating film, a source and a drain. The source and the drain are formed in a first area of a semiconductor substrate. A first silicon oxide film is formed on a second area of the semiconductor substrate adjacent to the first area. The first silicon oxide film is thicker than the gate insulating film and contains larger amount of impurities than the gate insulating film. A poly-silicon layer is formed on the first silicon oxide film. The protection diode has a plurality of PN-junctions formed in the poly-silicon layer. The protection diode is connected between the gate electrode and the source so as to prevent breakdown of the gate insulating film.
摘要翻译：半导体器件包括绝缘栅场效应晶体管和保护二极管。绝缘栅场效应晶体管具有形成在栅极绝缘膜，源极和漏极上的栅电极。源极和漏极形成在半导体衬底的第一区域中。第一氧化硅膜形成在与第一区域相邻的半导体衬底的第二区域上。第一氧化硅膜比栅极绝缘膜厚，并且含有比栅极绝缘膜更大量的杂质。在第一氧化硅膜上形成多晶硅层。保护二极管具有形成在多晶硅层中的多个PN结。保护二极管连接在栅极和源极之间，以防止栅极绝缘膜破裂。

8. 发明授权

US07714383B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07714383B2
公开(公告)日：2010-05-11
申请号：US12258135
申请日：2008-10-24
申请人： Keiko Kawamura , Kenji Maeyama
发明人： Keiko Kawamura , Kenji Maeyama
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L27/088 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/407 , H01L29/66734 , H01L29/7813 , H01L29/861
摘要： A semiconductor device includes: a semiconductor layer, a first semiconductor region provided on a major surface of the semiconductor layer, a second semiconductor region provided in a surface portion of the first semiconductor region, a trench extending through the second semiconductor region and the first semiconductor region to the semiconductor layer, a first insulating film provided on an inner wall of the trench, a third semiconductor region filling the trench below an interface between the semiconductor layer and the first semiconductor region, a second insulating film provided on the third semiconductor region, a gate electrode filling the trench above the second insulating film. A portion of the first insulating film in contact with the semiconductor layer is opened. The semiconductor layer is in contact with the third semiconductor region through the opened portion.
摘要翻译：半导体器件包括：半导体层，设置在半导体层的主表面上的第一半导体区域，设置在第一半导体区域的表面部分中的第二半导体区域，延伸穿过第二半导体区域的沟槽和第一半导体设置在所述沟槽的内壁上的第一绝缘膜，在所述半导体层和所述第一半导体区域之间的界面下方填充所述沟槽的第三半导体区域，设置在所述第三半导体区域上的第二绝缘膜，栅电极填充第二绝缘膜上方的沟槽。与半导体层接触的第一绝缘膜的一部分被打开。半导体层通过开口部分与第三半导体区域接触。

9. 发明授权

US07541642B2 Semiconductor device with a gate electrode including a pair of polysilicon layers 失效
标题翻译：具有包括一对多晶硅层的栅电极的半导体器件
公开(公告)号：US07541642B2
公开(公告)日：2009-06-02
申请号：US11245042
申请日：2005-10-07
申请人： Keiko Kawamura , Masanobu Tsuchitani
发明人： Keiko Kawamura , Masanobu Tsuchitani
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/66727 , H01L29/66734 , H01L29/7397
摘要： A semiconductor device comprises a semiconductor substrate having a gate trench formed therein. A gate electrode is formed on a gate insulator in the gate trench. The gate electrode has ends close to the bottom of the gate trench, which are separated in a direction perpendicular to both sides of the gate trench, and portions except the separated ends, at least part of which is made higher in conductivity than other parts.
摘要翻译：半导体器件包括其中形成有栅极沟槽的半导体衬底。栅极电极形成在栅极沟槽中的栅极绝缘体上。栅电极具有靠近栅极沟槽的底部的端部，栅极沟槽的底部沿垂直于栅极沟槽两侧的方向分开，以及除了分离端部以外的部分，其至少一部分的导电率比其它部分高。

10. 发明申请

US20070023828A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070023828A1
公开(公告)日：2007-02-01
申请号：US11245042
申请日：2005-10-07
申请人： Keiko Kawamura , Masanobu Tsuchitani
发明人： Keiko Kawamura , Masanobu Tsuchitani
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/66727 , H01L29/66734 , H01L29/7397
摘要： A semiconductor device comprises a semiconductor substrate having a gate trench formed therein. A gate electrode is formed on a gate insulator in the gate trench. The gate electrode has ends close to the bottom of the gate trench, which are separated in a direction perpendicular to both sides of the gate trench, and portions except the separated ends, at least part of which is made higher in conductivity than other parts.
摘要翻译：半导体器件包括其中形成有栅极沟槽的半导体衬底。栅极电极形成在栅极沟槽中的栅极绝缘体上。栅电极具有靠近栅极沟槽的底部的端部，栅极沟槽的底部沿垂直于栅极沟槽两侧的方向分开，以及除了分离端部以外的部分，其至少一部分的导电率比其它部分高。

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