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1. 发明授权

US07983102B2 Data detecting apparatus and methods thereof 有权
标题翻译：数据检测装置及其方法
公开(公告)号：US07983102B2
公开(公告)日：2011-07-19
申请号：US12579920
申请日：2009-10-15
申请人： Shih-Hsing Wang , Der-Min Yuan , Bor-Doou Rong , Chun Shiah
发明人： Shih-Hsing Wang , Der-Min Yuan , Bor-Doou Rong , Chun Shiah
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08
摘要： A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.
摘要翻译：在本发明的实施例中公开了一种数据检测装置和数据检测方法。数据检测装置根据具有预定周期的时钟信号进行操作。数据检测装置包括多个存储单元，多个数据线，多个位线，多个读出放大器和预充电控制电路。

2. 发明申请

US20100103753A1 DATA DETECTING APPARATUS AND METHODS THEREOF 有权
标题翻译：数据检测装置及其方法
公开(公告)号：US20100103753A1
公开(公告)日：2010-04-29
申请号：US12579920
申请日：2009-10-15
申请人： Shih-Hsing WANG , Der-Min Yuan , Bor-Doou Rong , Chun Shiah
发明人： Shih-Hsing WANG , Der-Min Yuan , Bor-Doou Rong , Chun Shiah
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/12 , G11C7/08
摘要： A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.
摘要翻译：在本发明的实施例中公开了一种数据检测装置和数据检测方法。数据检测装置根据具有预定周期的时钟信号进行操作。数据检测装置包括多个存储单元，多个数据线，多个位线，多个读出放大器和预充电控制电路。

3. 发明授权

US06934899B2 Variable self-time scheme for write recovery by low speed tester 有权
标题翻译：低速测试仪写入恢复的可变自身时间方案
公开(公告)号：US06934899B2
公开(公告)日：2005-08-23
申请号：US10060481
申请日：2002-01-30
申请人： Der-Min Yuan , Bor-Doou Rong
发明人： Der-Min Yuan , Bor-Doou Rong
IPC分类号： G11C29/14 , G01R31/28 , G11C29/00
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/14
摘要： In accordance with the objectives of the invention a new method is provided for testing DRAM cells using a slow-speed tester. An adjustable self-time scheme is provided that is used for write-recovery during the testing of DRAM devices using a low-speed tester. CSL and WL pulses are self-time controlled and are in this manner used to emulate DRAM operation under different operational conditions. The adjustable self-time scheme of the invention can be used to screen write recovery (twr) depending on field requirements for the DRAM cell, a low-speed tester can be used for the screening.
摘要翻译：根据本发明的目的，提供了一种使用慢速测试仪测试DRAM单元的新方法。提供了一种可调节的自身时间方案，用于使用低速测试仪测试DRAM器件时的写恢复。 CSL和WL脉冲是自我时间控制的，并且以这种方式用于在不同的操作条件下模拟DRAM操作。根据DRAM单元的场要求，可以使用本发明的可调节自定时方案来屏蔽写恢复（twr），可以使用低速测试器进行筛选。

4. 发明授权

US07515669B2 Dynamic input setup/hold time improvement architecture 有权
标题翻译：动态输入设置/保持时间改进架构
公开(公告)号：US07515669B2
公开(公告)日：2009-04-07
申请号：US11227847
申请日：2005-09-15
申请人： Chun Shiah , Bor-Doou Rong , Shi-Huei Liu
发明人： Chun Shiah , Bor-Doou Rong , Shi-Huei Liu
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03K19/0027 , H04L7/0041
摘要： A new method to sample a digital input signal is achieved. The method comprises sampling a digital input processed through a first digital buffer. The sampling is at the rising edge of a system clock. The switching threshold of a second digital buffer is updated. The digital input processed through the second digital buffer is sampled. The sampling is at the falling edge of the system clock. The switching threshold of the first digital buffer is updated. A digital sampling circuit is achieved.
摘要翻译：实现了一种采样数字输入信号的新方法。该方法包括对通过第一数字缓冲器处理的数字输入进行采样。采样位于系统时钟的上升沿。更新第二数字缓冲器的切换阈值。对通过第二数字缓冲器处理的数字输入进行采样。采样位于系统时钟的下降沿。更新第一数字缓冲器的切换阈值。实现数字采样电路。

5. 发明申请

US20070058765A1 Dynamic input setup/hold time improvement architecture 有权
标题翻译：动态输入设置/保持时间改进架构
公开(公告)号：US20070058765A1
公开(公告)日：2007-03-15
申请号：US11227847
申请日：2005-09-15
申请人： Chun Shiah , Bor-Doou Rong , Shi-Huei Liu
发明人： Chun Shiah , Bor-Doou Rong , Shi-Huei Liu
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03K19/0027 , H04L7/0041
摘要： A new method to sample a digital input signal is achieved. The method comprises sampling a digital input processed through a first digital buffer. The sampling is at the rising edge of a system clock. The switching threshold of a second digital buffer is updated. The digital input processed through the second digital buffer is sampled. The sampling is at the falling edge of the system clock. The switching threshold of the first digital buffer is updated. A digital sampling circuit is achieved.
摘要翻译：实现了一种采样数字输入信号的新方法。该方法包括对通过第一数字缓冲器处理的数字输入进行采样。采样位于系统时钟的上升沿。更新第二数字缓冲器的切换阈值。对通过第二数字缓冲器处理的数字输入进行采样。采样位于系统时钟的下降沿。更新第一数字缓冲器的切换阈值。实现数字采样电路。

6. 发明授权

US06101138A Area efficient global row redundancy scheme for DRAM 有权
标题翻译：用于DRAM的区域有效的全局行冗余方案
公开(公告)号：US06101138A
公开(公告)日：2000-08-08
申请号：US358982
申请日：1999-07-22
申请人： Chun Shiah , Bor-Doou Rong , Jeng-Tzong Shih , Po-Hung Chen
发明人： Chun Shiah , Bor-Doou Rong , Jeng-Tzong Shih , Po-Hung Chen
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808
摘要： In this invention a global row redundancy scheme for a DRAM is described which effectively uses the resources of the chip to produce an area efficient design. The DRAM is constructed from two types of memory blocks, one that has a redundant cell array and one that does not. Both memory block types contain a memory cell array and bit line sense amplifiers. The bit line sense amplifiers, contained on the block with the redundant cell array, are shared with the memory cell array also contained in the block, and thus eliminating the need for sense amplifiers for use only with the redundant cell array. Although, every block could contain a redundant cell array, only one or two blocks with the redundant cell array are normally used. In the global row redundancy scheme repair can be made to any row containing a failed memory cell located in any memory block by using any unused rows in any redundant cell array, and in doing so provides a maximum effectiveness in repairing DRAM's that provides the opportunity to maximize yield.
摘要翻译：在本发明中，描述了用于DRAM的全局行冗余方案，其有效地使用芯片的资源来产生区域有效的设计。 DRAM由两种类型的存储器块构成，一个具有冗余单元阵列，另一个不存在。这两种存储块类型都包含存储单元阵列和位线读出放大器。包含在具有冗余单元阵列的块上的位线读出放大器与也包含在该块中的存储单元阵列共享，因此不需要仅用于冗余单元阵列的读出放大器。尽管每个块都可以包含冗余单元阵列，但通常只使用一个或两个具有冗余单元阵列的块。在全局行冗余方案中，可以通过使用任何冗余单元阵列中的任何未使用的行来修复任何包含位于任何存储器块中的故障存储器单元的行，并且这样做可以提供修复提供机会的DRAM的最大有效性最大化产量。

7. 发明授权

US5723994A Level boost restoration circuit 失效
标题翻译：电平升压恢复电路
公开(公告)号：US5723994A
公开(公告)日：1998-03-03
申请号：US661288
申请日：1996-06-10
申请人： Tah-Kang Joseph Ting , Chun Shiah , Bor-Doou Rong
发明人： Tah-Kang Joseph Ting , Chun Shiah , Bor-Doou Rong
IPC分类号： H03K19/003 , H03K19/017 , H03K7/08
CPC分类号： H03K19/00361 , H03K19/01721
摘要： A spurious glitch elongation circuit is described. The spurious glitch elongation circuit will allow the restoration of the output level of a level boost driving circuit. The circuit has a one-sided delay chain to increase the pulse width of spurious glitches that are from one logic state to a second logic state and return to the first logic state, while minimizing spurious glitches that are from the second logic state to the first logic state and returned to the second logic state.
摘要翻译：描述了假毛刺延长电路。假毛刺延长电路将允许恢复升压驱动电路的输出电平。该电路具有单向延迟链，以增加从一个逻辑状态到第二逻辑状态的伪脉冲的脉冲宽度，并返回到第一逻辑状态，同时将从第二逻辑状态到第一逻辑状态的假毛刺最小化逻辑状态并返回到第二个逻辑状态。

8. 发明授权

US06661719B1 Wafer level burn-in for memory integrated circuit 有权
标题翻译：晶圆级老化用于存储器集成电路
公开(公告)号：US06661719B1
公开(公告)日：2003-12-09
申请号：US10193444
申请日：2002-07-11
申请人： Jeng-Tzong Shih , Shi-Huei Liu , Bor-Doou Rong
发明人： Jeng-Tzong Shih , Shi-Huei Liu , Bor-Doou Rong
IPC分类号： G11C700
CPC分类号： G11C29/34 , G11C29/006 , G11C2029/1202 , G11C2029/2602
摘要： A memory device with burn-in capability is achieved. The device comprises, first, an array of memory cells, and, second, a burn-in test block. The burn-in test block comprises a memory address generator, a data pattern generator, and a command pattern generator. The burn-in test block is capable of writing data to the memory cells, of turning ON word lines in the array, and of holding the array in a static mode. A method to perform wafer level burn-in with this device is disclosed.
摘要翻译：实现了具有老化能力的存储器件。该装置首先包括一组存储器单元，其次，包括一个老化测试块。老化测试块包括存储器地址发生器，数据模式发生器和命令模式发生器。老化测试块能够将数据写入存储单元，打开阵列中的字线，并将阵列保持在静态模式。公开了一种用该装置执行晶片级老化的方法。

9. 发明授权

US07478294B2 Time controllable sensing scheme for sense amplifier in memory IC test 有权
标题翻译：用于存储器IC测试的读出放大器的时间可控感测方案
公开(公告)号：US07478294B2
公开(公告)日：2009-01-13
申请号：US11152476
申请日：2005-06-14
申请人： Bor-Doou Rong , Shi-Huei Liu
发明人： Bor-Doou Rong , Shi-Huei Liu
IPC分类号： G01R31/28
CPC分类号： G11C29/02 , G11C29/025 , G11C29/56012 , G11C2029/5006
摘要： A test method is described in which a signal from a tester enters a memory chip or memory module into a special test mode. The special test mode allows leakage defects connected to bit lines to be detected using bit line sense amplifiers. A first test command is issued by a tester, after which a word line is activated. The tester issues a second test command, delayed from the first test command, during the special test mode to turn-on the memory bit line sense amplifiers. The delayed second test command allows sufficient time for the leakage from defects at the crossing of the bit lines and the word line to charge capacitance of the bit lines and allow detection by the sense amplifiers.
摘要翻译：描述了一种测试方法，其中来自测试者的信号进入存储器芯片或存储器模块进入特殊测试模式。特殊测试模式允许使用位线读出放大器检测连接到位线的泄漏缺陷。第一个测试命令由测试仪发出，之后激活了一个字线。在特殊测试模式下，测试仪发出第二个测试命令，从第一个测试命令延迟，以打开存储器位线读出放大器。延迟的第二测试命令允许足够的时间从位线和字线的交叉处的缺陷泄漏以对位线的电容进行充电，并允许读出放大器进行检测。

10. 发明授权

US06643166B1 Low power SRAM redundancy repair scheme 有权
标题翻译：低功耗SRAM冗余修复方案
公开(公告)号：US06643166B1
公开(公告)日：2003-11-04
申请号：US09992518
申请日：2001-11-14
申请人： Tah-Kang Joseph Ting , Bor-Doou Rong , Shi-Huei Liu
发明人： Tah-Kang Joseph Ting , Bor-Doou Rong , Shi-Huei Liu
IPC分类号： G11C1100
CPC分类号： G11C29/83 , G11C29/832
摘要： A particular SRAM cell power scheme is disclosed. It ensures that overall chip power is reduced, by eliminating power contributed by defective memory array cells. The VSS path to the 6T memory cell is controlled via NMOS transistors. A VSS Enable (VSSEN) circuit is used to decode which block has a defect. Further, the VSSEN signal can be used to selectively disable a defective cell, or block of cells, by cutting the VSS path via turning off the NMOS transistor, in the normal cell region, and the VSSEN signal can be used to selectively enable a redundant cell, or block of cells, by turning on the VSS path via turning on the NMOS transistor, in the redundant cell region.
摘要翻译：公开了一种特定的SRAM单元电力方案。通过消除由缺陷存储器阵列单元造成的功率，可以确保整体芯片功耗的降低。通过NMOS晶体管控制到6T存储单元的VSS通路。 VSS使能（VSSEN）电路用于解码哪个块有缺陷。此外，VSSEN信号可用于通过在正常单元区域中关断NMOS晶体管来切断VSS路径来选择性地禁用故障单元或单元块，并且可使用VSSEN信号选择性地使能冗余通过在冗余单元区域中导通NMOS晶体管来导通VSS路径，从而使单元或单元块成为可能。

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