专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06661719B1 Wafer level burn-in for memory integrated circuit 有权
标题翻译：晶圆级老化用于存储器集成电路
公开(公告)号：US06661719B1
公开(公告)日：2003-12-09
申请号：US10193444
申请日：2002-07-11
申请人： Jeng-Tzong Shih , Shi-Huei Liu , Bor-Doou Rong
发明人： Jeng-Tzong Shih , Shi-Huei Liu , Bor-Doou Rong
IPC分类号： G11C700
CPC分类号： G11C29/34 , G11C29/006 , G11C2029/1202 , G11C2029/2602
摘要： A memory device with burn-in capability is achieved. The device comprises, first, an array of memory cells, and, second, a burn-in test block. The burn-in test block comprises a memory address generator, a data pattern generator, and a command pattern generator. The burn-in test block is capable of writing data to the memory cells, of turning ON word lines in the array, and of holding the array in a static mode. A method to perform wafer level burn-in with this device is disclosed.
摘要翻译：实现了具有老化能力的存储器件。该装置首先包括一组存储器单元，其次，包括一个老化测试块。老化测试块包括存储器地址发生器，数据模式发生器和命令模式发生器。老化测试块能够将数据写入存储单元，打开阵列中的字线，并将阵列保持在静态模式。公开了一种用该装置执行晶片级老化的方法。

2. 发明授权

US07478294B2 Time controllable sensing scheme for sense amplifier in memory IC test 有权
标题翻译：用于存储器IC测试的读出放大器的时间可控感测方案
公开(公告)号：US07478294B2
公开(公告)日：2009-01-13
申请号：US11152476
申请日：2005-06-14
申请人： Bor-Doou Rong , Shi-Huei Liu
发明人： Bor-Doou Rong , Shi-Huei Liu
IPC分类号： G01R31/28
CPC分类号： G11C29/02 , G11C29/025 , G11C29/56012 , G11C2029/5006
摘要： A test method is described in which a signal from a tester enters a memory chip or memory module into a special test mode. The special test mode allows leakage defects connected to bit lines to be detected using bit line sense amplifiers. A first test command is issued by a tester, after which a word line is activated. The tester issues a second test command, delayed from the first test command, during the special test mode to turn-on the memory bit line sense amplifiers. The delayed second test command allows sufficient time for the leakage from defects at the crossing of the bit lines and the word line to charge capacitance of the bit lines and allow detection by the sense amplifiers.
摘要翻译：描述了一种测试方法，其中来自测试者的信号进入存储器芯片或存储器模块进入特殊测试模式。特殊测试模式允许使用位线读出放大器检测连接到位线的泄漏缺陷。第一个测试命令由测试仪发出，之后激活了一个字线。在特殊测试模式下，测试仪发出第二个测试命令，从第一个测试命令延迟，以打开存储器位线读出放大器。延迟的第二测试命令允许足够的时间从位线和字线的交叉处的缺陷泄漏以对位线的电容进行充电，并允许读出放大器进行检测。

3. 发明授权

US06643166B1 Low power SRAM redundancy repair scheme 有权
标题翻译：低功耗SRAM冗余修复方案
公开(公告)号：US06643166B1
公开(公告)日：2003-11-04
申请号：US09992518
申请日：2001-11-14
申请人： Tah-Kang Joseph Ting , Bor-Doou Rong , Shi-Huei Liu
发明人： Tah-Kang Joseph Ting , Bor-Doou Rong , Shi-Huei Liu
IPC分类号： G11C1100
CPC分类号： G11C29/83 , G11C29/832
摘要： A particular SRAM cell power scheme is disclosed. It ensures that overall chip power is reduced, by eliminating power contributed by defective memory array cells. The VSS path to the 6T memory cell is controlled via NMOS transistors. A VSS Enable (VSSEN) circuit is used to decode which block has a defect. Further, the VSSEN signal can be used to selectively disable a defective cell, or block of cells, by cutting the VSS path via turning off the NMOS transistor, in the normal cell region, and the VSSEN signal can be used to selectively enable a redundant cell, or block of cells, by turning on the VSS path via turning on the NMOS transistor, in the redundant cell region.
摘要翻译：公开了一种特定的SRAM单元电力方案。通过消除由缺陷存储器阵列单元造成的功率，可以确保整体芯片功耗的降低。通过NMOS晶体管控制到6T存储单元的VSS通路。 VSS使能（VSSEN）电路用于解码哪个块有缺陷。此外，VSSEN信号可用于通过在正常单元区域中关断NMOS晶体管来切断VSS路径来选择性地禁用故障单元或单元块，并且可使用VSSEN信号选择性地使能冗余通过在冗余单元区域中导通NMOS晶体管来导通VSS路径，从而使单元或单元块成为可能。

4. 发明授权

US06377492B1 Memory architecture for read and write at the same time using a conventional cell 有权
标题翻译：使用传统单元同时进行读写的内存架构
公开(公告)号：US06377492B1
公开(公告)日：2002-04-23
申请号：US09809839
申请日：2001-03-19
申请人： Bor-Doou Rong , Ghy-Bin Wang
发明人： Bor-Doou Rong , Ghy-Bin Wang
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C7/18 , G11C8/16
摘要： A simultaneous read and write memory is shown. The memory is configured into a plurality of sections. Connected to each section is a wordline multiplexer which is used to select a wordline for reading or writing. A write wordline decoder and a read wordline decoder are each connected to all the wordline multiplexers. The multiplexers choose either a write wordline or a read wordline independently for each memory section. A write data path and a read data path are separately connected to each of the memory sections. With the separate write and read wordline addressing and the separate data paths for reading and writing, one section can be written simultaneous to the reading from a second section.
摘要翻译：显示同时的读写存储器。存储器被配置成多个部分。连接到每个部分是字线多路复用器，用于选择用于读取或写入的字线。写字字解码器和读字字解码器各自连接到所有字线复用器。多路复用器为每个存储器部分独立地选择写字线或读字线。写入数据路径和读取数据路径分别连接到每个存储器部分。通过单独的写入和读取字线寻址以及用于读取和写入的单独数据路径，可以将一个部分与第二个部分的读取同时写入。

5. 发明申请

US20100103753A1 DATA DETECTING APPARATUS AND METHODS THEREOF 有权
标题翻译：数据检测装置及其方法
公开(公告)号：US20100103753A1
公开(公告)日：2010-04-29
申请号：US12579920
申请日：2009-10-15
申请人： Shih-Hsing WANG , Der-Min Yuan , Bor-Doou Rong , Chun Shiah
发明人： Shih-Hsing WANG , Der-Min Yuan , Bor-Doou Rong , Chun Shiah
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/12 , G11C7/08
摘要： A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.
摘要翻译：在本发明的实施例中公开了一种数据检测装置和数据检测方法。数据检测装置根据具有预定周期的时钟信号进行操作。数据检测装置包括多个存储单元，多个数据线，多个位线，多个读出放大器和预充电控制电路。

6. 发明申请

US20080202800A1 Re-routing method and the circuit thereof 审中-公开
标题翻译：重路由方法及其电路
公开(公告)号：US20080202800A1
公开(公告)日：2008-08-28
申请号：US12149055
申请日：2008-04-25
申请人： Ming-Hong Kuo , Bor-Doou Rong , Yi-Chen Wu , Hsin-I Cheng
发明人： Ming-Hong Kuo , Bor-Doou Rong , Yi-Chen Wu , Hsin-I Cheng
IPC分类号： H05K1/09
CPC分类号： G01R31/31723 , H01L24/06
摘要： A re-routing method and the circuit thereof, used to rearrange the external circuit coupled with the integrated circuit (IC), comprises the steps of providing a plurality of first conductive plate on the substrate of the IC to form an isolation layer; providing a plurality of second conductive plates on the isolation layer, wherein each of the second conductive plates is moved in isovector with each of the corresponding first conductive plates as the center, each of the second conductive plates electrically connected with each of the first conductive plates. Therefore, according to move the second conductive plates in isovector, the probe card may be reused for circuit testing to save the cost and reduce the material management.
摘要翻译：用于重排与集成电路（IC）耦合的外部电路的重路由方法及其电路包括以下步骤：在IC的基板上提供多个第一导电板以形成隔离层; 在所述隔离层上设置多个第二导电板，其中每个所述第二导电板在所述对应的第一导电板中的每一个的移动体中移动，所述第二导电板中的每一个与所述第一导电板。因此，根据移动器中的第二导电板，探针卡可以重新用于电路测试以节省成本并减少材料管理。

7. 发明申请

US20070140308A1 Calibrated built-in temperature sensor and calibration method thereof 有权
标题翻译：校准的内置温度传感器及其校准方法
公开(公告)号：US20070140308A1
公开(公告)日：2007-06-21
申请号：US11304881
申请日：2005-12-16
申请人： Jen-Shou Hsu , Bor-Doou Rong
发明人： Jen-Shou Hsu , Bor-Doou Rong
IPC分类号： G01K15/00
CPC分类号： G01K15/00 , G01K7/01
摘要： A built-in calibration device is for a temperature sensor. A voltage divider is configured for receiving one reference voltage with a negative temperature coefficient and generating a plurality of input voltages. Comparing apparatus is connected to the voltage divider and configured for generating a plurality of comparing codes based upon another reference voltage with a positive temperature coefficient and the plurality of input voltages. Controlling apparatus is connected to the comparing apparatus and configured for calibrating the temperature sensor based on the plurality of comparing codes.
摘要翻译：内置校准装置用于温度传感器。分压器被配置为接收具有负温度系数的一个参考电压并产生多个输入电压。比较装置连接到分压器，并被配置为基于具有正温度系数和多个输入电压的另一个参考电压产生多个比较代码。控制装置连接到比较装置并且被配置为基于多个比较代码校准温度传感器。

8. 发明申请

US20070058765A1 Dynamic input setup/hold time improvement architecture 有权
标题翻译：动态输入设置/保持时间改进架构
公开(公告)号：US20070058765A1
公开(公告)日：2007-03-15
申请号：US11227847
申请日：2005-09-15
申请人： Chun Shiah , Bor-Doou Rong , Shi-Huei Liu
发明人： Chun Shiah , Bor-Doou Rong , Shi-Huei Liu
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03K19/0027 , H04L7/0041
摘要： A new method to sample a digital input signal is achieved. The method comprises sampling a digital input processed through a first digital buffer. The sampling is at the rising edge of a system clock. The switching threshold of a second digital buffer is updated. The digital input processed through the second digital buffer is sampled. The sampling is at the falling edge of the system clock. The switching threshold of the first digital buffer is updated. A digital sampling circuit is achieved.
摘要翻译：实现了一种采样数字输入信号的新方法。该方法包括对通过第一数字缓冲器处理的数字输入进行采样。采样位于系统时钟的上升沿。更新第二数字缓冲器的切换阈值。对通过第二数字缓冲器处理的数字输入进行采样。采样位于系统时钟的下降沿。更新第一数字缓冲器的切换阈值。实现数字采样电路。

9. 发明申请

US20060028228A1 Test pads for IC chip 审中-公开
标题翻译： IC芯片测试垫
公开(公告)号：US20060028228A1
公开(公告)日：2006-02-09
申请号：US10911425
申请日：2004-08-05
申请人： Bor-Doou Rong
发明人： Bor-Doou Rong
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： The testing pads for multi-chip package are alternately placed at two ends or open area of the chip, so that the spacing between the test pads is wide enough for test probes to access.
摘要翻译：用于多芯片封装的测试焊盘交替放置在芯片的两端或开放区域，使得测试焊盘之间的间距足够宽，以便测试探头访问。

10. 发明申请

US20060012418A1 Low power design for fuse control circuit 有权
公开(公告)号：US20060012418A1
公开(公告)日：2006-01-19
申请号：US10889910
申请日：2004-07-13
申请人： Jeng-Tzong Shih , Bor-Doou Rong
发明人： Jeng-Tzong Shih , Bor-Doou Rong
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A blocking section is inserted between the control section and the fuse section of a fuse control logic circuit. The blocking section comprises switching means which block the flow of DC current during a power-up sequence and thus avoids the collapse of the power supply voltage with the attending potential for incorrect addressing and improper function and timing options. The insertion of the blocking section further eliminates indeterminate logic states when fusible means are not fully blown thus assuring correct voltage levels at the output of the circuit.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式