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1. 发明授权

US08345500B2 Memory having a disabling circuit and method for disabling the memory 有权
标题翻译：具有禁用电路的存储器和用于禁止存储器的方法
公开(公告)号：US08345500B2
公开(公告)日：2013-01-01
申请号：US12912748
申请日：2010-10-27
申请人： Shih-Hsing Wang , Der-Min Yuan
发明人： Shih-Hsing Wang , Der-Min Yuan
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , G11C29/006 , G11C29/1201 , G11C29/832
摘要： A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix.
摘要翻译：具有禁用电路的存储器包括存储器矩阵和禁用电路。存储器矩阵包括数据输入/输出端和输出使能端。禁用电路包括保险丝和输出端。当保险丝不熔断时，禁用电路根据输出使能端的信号将数据输入/输出端的信号发送到输出端。当保险丝熔断时，禁用电路在输出端产生三态。因此，外部电路不能执行读取或写入操作以访问存储器矩阵。

2. 发明授权

US07983102B2 Data detecting apparatus and methods thereof 有权
标题翻译：数据检测装置及其方法
公开(公告)号：US07983102B2
公开(公告)日：2011-07-19
申请号：US12579920
申请日：2009-10-15
申请人： Shih-Hsing Wang , Der-Min Yuan , Bor-Doou Rong , Chun Shiah
发明人： Shih-Hsing Wang , Der-Min Yuan , Bor-Doou Rong , Chun Shiah
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08
摘要： A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.
摘要翻译：在本发明的实施例中公开了一种数据检测装置和数据检测方法。数据检测装置根据具有预定周期的时钟信号进行操作。数据检测装置包括多个存储单元，多个数据线，多个位线，多个读出放大器和预充电控制电路。

3. 发明申请

US20080048727A1 Sense amplifier-based latch 审中-公开
标题翻译：基于放大器的锁存器
公开(公告)号：US20080048727A1
公开(公告)日：2008-02-28
申请号：US11808865
申请日：2007-06-13
申请人： Der-Min Yuan , Shih-Hsing Wang
发明人： Der-Min Yuan , Shih-Hsing Wang
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C7/065 , G11C7/1051 , G11C7/1087 , G11C11/4091 , G11C11/4093
摘要： A sense amplifier-based latch is provided. It comprises an input circuit, a sense amplifier, a latch circuit and an output circuit. By employing the latch circuit, the variation frequency of an output signal and a complementary output signal as well as lots of charge consumption is reduced. Accordingly, the invention has less glitches and malfunctions, thus suitable for high-speed circuit applications.
摘要翻译：提供基于读出放大器的锁存器。它包括输入电路，读出放大器，锁存电路和输出电路。通过采用锁存电路，减少了输出信号和互补输出信号的变化频率以及大量的电荷消耗。因此，本发明具有较少的毛刺和故障，因此适用于高速电路应用。

4. 发明申请

US20050243613A1 Method of high speed data rate testing 有权
公开(公告)号：US20050243613A1
公开(公告)日：2005-11-03
申请号：US11174859
申请日：2005-07-05
申请人： Tah-Kang Joseph Ting , Shih-Hsing Wang , Hong-Jie Chen
发明人： Tah-Kang Joseph Ting , Shih-Hsing Wang , Hong-Jie Chen
IPC分类号： G11C5/00 , H01L21/66
CPC分类号： G01R31/31922 , G11C11/40 , G11C29/006 , G11C29/023 , G11C2029/5602
摘要： A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.

5. 发明授权

US08125838B2 System in package integrated circuit with self-generating reference voltage 有权
标题翻译：具有自产生参考电压的封装集成电路系统
公开(公告)号：US08125838B2
公开(公告)日：2012-02-28
申请号：US12892934
申请日：2010-09-29
申请人： Shih-Hsing Wang , Der-Min Yuan
发明人： Shih-Hsing Wang , Der-Min Yuan
IPC分类号： G11C7/06
CPC分类号： G11C7/1006 , G11C2207/104
摘要： This invention provides a system in package integrated circuit with self-generating reference voltage, in which includes a logic circuit chip and a memory chip. The logic circuit chip generates a plurality of output signals, and the memory chip includes a plurality of input circuit receiving the plurality of output signals from the logic circuit chip. The memory chip further includes a voltage generator generating an input reference voltage based on an output supply voltage. The memory chip is compatible with DDR standard and the plurality of input circuit thereof is compatible with SSTL_2 standard. Wherein, each input circuit comprises a comparator with a first input terminal receiving one of the plurality of output signals and a second input terminal receiving the input reference voltage.
摘要翻译：本发明提供具有自产生参考电压的封装集成电路系统，其中包括逻辑电路芯片和存储器芯片。逻辑电路芯片产生多个输出信号，并且存储器芯片包括从逻辑电路芯片接收多个输出信号的多个输入电路。存储器芯片还包括基于输出电源电压产生输入参考电压的电压发生器。内存芯片与DDR标准兼容，其多个输入电路与SSTL_2标准兼容。其中，每个输入电路包括具有接收多个输出信号中的一个的第一输入端的比较器和接收输入参考电压的第二输入端。

6. 发明申请

US20110176381A1 MEMORY HAVING A DISABLING CIRCUIT AND METHOD FOR DISABLING THE MEMORY 有权
标题翻译：具有禁用电路的存储器和用于禁止存储器的方法
公开(公告)号：US20110176381A1
公开(公告)日：2011-07-21
申请号：US12912748
申请日：2010-10-27
申请人： Shih-Hsing Wang , Der-Min Yuan
发明人： Shih-Hsing Wang , Der-Min Yuan
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C17/18 , G11C29/006 , G11C29/1201 , G11C29/832
摘要： A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix.
摘要翻译：具有禁用电路的存储器包括存储器矩阵和禁用电路。存储器矩阵包括数据输入/输出端和输出使能端。禁用电路包括保险丝和输出端。当保险丝不熔断时，禁用电路根据输出使能端的信号将数据输入/输出端的信号发送到输出端。当保险丝熔断时，禁用电路在输出端产生三态。因此，外部电路不能执行读取或写入操作以访问存储器矩阵。

7. 发明申请

US20110085388A1 SYSTEM IN PACKAGE INTEGRATED CIRCUIT WITH SELF-GENERATING REFERENCE VOLTAGE 有权
标题翻译：具有自产生参考电压的封装集成电路系统
公开(公告)号：US20110085388A1
公开(公告)日：2011-04-14
申请号：US12892934
申请日：2010-09-29
申请人： Shih-Hsing Wang , Der-Min Yuan
发明人： Shih-Hsing Wang , Der-Min Yuan
IPC分类号： G11C7/06
CPC分类号： G11C7/1006 , G11C2207/104
摘要： This invention provides a system in package integrated circuit with self-generating reference voltage, in which includes a logic circuit chip and a memory chip. The logic circuit chip generates a plurality of output signals, and the memory chip includes a plurality of input circuit receiving the plurality of output signals from the logic circuit chip. The memory chip further includes a voltage generator generating an input reference voltage based on an output supply voltage. The memory chip is compatible with DDR standard and the plurality of input circuit thereof is compatible with SSTL_2 standard. Wherein, each input circuit comprises a comparator with a first input terminal receiving one of the plurality of output signals and a second input terminal receiving the input reference voltage.
摘要翻译：本发明提供具有自产生参考电压的封装集成电路系统，其中包括逻辑电路芯片和存储器芯片。逻辑电路芯片产生多个输出信号，并且存储器芯片包括从逻辑电路芯片接收多个输出信号的多个输入电路。存储器芯片还包括基于输出电源电压产生输入参考电压的电压发生器。内存芯片与DDR标准兼容，其多个输入电路与SSTL_2标准兼容。其中，每个输入电路包括具有接收多个输出信号中的一个的第一输入端的比较器和接收输入参考电压的第二输入端。

8. 发明授权

US07475305B2 Method of high speed data rate testing 有权
标题翻译：高速数据速率测试方法
公开(公告)号：US07475305B2
公开(公告)日：2009-01-06
申请号：US11174859
申请日：2005-07-05
申请人： Tah-Kang Joseph Ting , Shih-Hsing Wang , Hong-Jie Chen
发明人： Tah-Kang Joseph Ting , Shih-Hsing Wang , Hong-Jie Chen
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/31922 , G11C11/40 , G11C29/006 , G11C29/023 , G11C2029/5602
摘要： A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.
摘要翻译：一种优化多电路数据选通的方法，实现了自动测试系统。该方法包括：首先并行地探测电路组，其中电路组包括多个电路。接下来，相对于系统时钟周期，自动测试系统的数据选通被初始化为选通设置点。接下来，使用频闪设定点并行地对每个电路的功能进行部分测试。接下来，记录在选通设定点的部分测试步骤中的电路组的电路产量。接下来，数据选通被更新为新的选通设定点。接下来，重复测试，记录和更新的步骤，直到指定的频闪设置点的范围完成。最后，将数据选通电路设置为电路组与最高电路产量相关的选通设定点。

9. 发明申请

US20080181028A1 Data flow scheme for low power DRAM 有权
标题翻译：低功耗DRAM的数据流方案
公开(公告)号：US20080181028A1
公开(公告)日：2008-07-31
申请号：US12079512
申请日：2008-03-27
申请人： Der-Min Yuan , Shih-Hsing Wang
发明人： Der-Min Yuan , Shih-Hsing Wang
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/14 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4099 , G11C2207/2227
摘要： Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation.
摘要翻译：已经实现了用于最小化DRAM感测和预充电所需功率的电路和方法。控制电路确保在读操作期间，将DRAM单元和预充电的感测持续时间保持在最小。测试DRAM单元用于确定数据检测所需的准确时间。此外，在写操作期间不进行预充电。如果数据从“1”变为“0”，反之亦然，在写操作期间相应地反转数据线。

10. 发明授权

US07924641B2 Data flow scheme for low power DRAM 有权
公开(公告)号：US07924641B2
公开(公告)日：2011-04-12
申请号：US12079446
申请日：2008-03-27
申请人： Der-Min Yuan , Shih-Hsing Wang
发明人： Der-Min Yuan , Shih-Hsing Wang
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/14 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4099 , G11C2207/2227
摘要： Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation.

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