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1. 发明授权

US4465342A Zoom lens 失效
标题翻译：变焦镜头
公开(公告)号：US4465342A
公开(公告)日：1984-08-14
申请号：US285012
申请日：1981-07-20
申请人： Kazuo Tanaka , Shigeyuki Suda
发明人： Kazuo Tanaka , Shigeyuki Suda
IPC分类号： G02B13/18 , G02B15/163 , G02B15/173 , G02B15/14
CPC分类号： G02B13/18 , G02B15/173
摘要： A zoom lens comprising, from front to rear, a first lens component having a positive focal length, a second lens component having a negative focal length and a third group having a positive focal length, the first and second lens components being moved to effect zooming, and the first lens component being moved to effect focusing. The above-described first, second and third lens components are each provided with at least one aspheric lens. The first lens component has a negative third order aspheric quantity and the second lens component has a positive third order aspheric quantity to realize a zoom lens of high imaging performance with fewer constituent lens elements.
摘要翻译：一种变焦透镜，包括从前到后具有正焦距的第一透镜部件，具有负焦距的第二透镜部件和具有正焦距的第三组，所述第一和第二透镜部件被移动以实现变焦并且第一透镜部件被移动以实现聚焦。上述第一，第二和第三透镜部件各自设置有至少一个非球面透镜。第一透镜部件具有负三阶非球面量，并且第二透镜部件具有正三阶非球面数量，以实现具有较少成分透镜元件的高成像性能的变焦透镜。

2. 发明授权

US4380376A Zoom objective 失效
标题翻译：缩放目标
公开(公告)号：US4380376A
公开(公告)日：1983-04-19
申请号：US159492
申请日：1980-06-16
申请人： Shigeyuki Suda , Kazuo Tanaka
发明人： Shigeyuki Suda , Kazuo Tanaka
IPC分类号： G02B15/20 , G02B15/173 , G02B15/18
CPC分类号： G02B15/173
摘要： A zoom objective is composed of three components of which the first and the third each perform a one-round axial movement over the range of variation, while the second simultaneously performs a monotonic axial movement in one direction.
摘要翻译：缩放目标由三个部件组成，其中第一和第三部件在变化范围上执行单向轴向运动，而第二部件同时在一个方向上执行单调轴向运动。

3. 发明授权

US08973253B2 Method and apparatus for manufacturing metal plate chip resistors 有权
标题翻译：制造金属板片式电阻器的方法和装置
公开(公告)号：US08973253B2
公开(公告)日：2015-03-10
申请号：US14074858
申请日：2013-11-08
申请人： Tatsuki Hirano , Kazuo Tanaka
发明人： Tatsuki Hirano , Kazuo Tanaka
IPC分类号： H01C17/00 , H01C17/245
CPC分类号： H01C17/006 , H01C17/245
摘要： The object of the invention is to provide a method and an apparatus that allow production of metal plate chip resistors having a relatively low resistance with high accuracy and yield through simple process. The object is achieved by apparatus for manufacturing metal plate chip resistors including cutting mold for cutting intermediate product strip transversely to obtain worked product chip, ohm meter for measuring the resistance of the worked product chip, control device having a calculating part for performing a calculation using the resistance measured by the ohm meter to work out a width in which the strip is to be cut transversely so as to obtain a worked product chip of a desired resistance, and cutting width adjustor for making an adjustment so that the strip is to be cut transversely in the width obtained from the calculating part.
摘要翻译：本发明的目的是提供一种通过简单的工艺制造具有相对较低电阻的金属板片式电阻器的方法和装置，其具有高精度和高产率。该目的是通过用于制造金属板片电阻器的装置实现的，包括用于横向切割中间产品带的切割模具，以获得加工产品芯片，用于测量加工产品芯片的电阻的欧姆表，具有用于执行计算的计算部分的控制装置由欧姆计测量的电阻以横向切割条的宽度，以获得期望电阻的加工产品芯片，以及用于进行调整的切割宽度调节器，使得条被切割横向于从计算部分获得的宽度。

4. 发明授权

US08590141B2 Method and apparatus for manufacturing metal plate chip resistors 有权
标题翻译：制造金属板片式电阻器的方法和装置
公开(公告)号：US08590141B2
公开(公告)日：2013-11-26
申请号：US13196078
申请日：2011-08-02
申请人： Tatsuki Hirano , Kazuo Tanaka
发明人： Tatsuki Hirano , Kazuo Tanaka
IPC分类号： H01C17/00
CPC分类号： H01C17/006 , H01C17/245
摘要： The object of the invention is to provide a method and an apparatus that allow production of metal plate chip resistors having a relatively low resistance with high accuracy and yield through simple process. The object is achieved by apparatus 10 for manufacturing metal plate chip resistors including cutting mold 21 for cutting intermediate product strip 14 transversely to obtain worked product chip 16a, ohm meter 22 for measuring the resistance of the worked product chip 16a, control device 23 having a calculating part for performing a calculation using the resistance measured by the ohm meter 22 to work out a width in which the strip 14 is to be cut transversely so as to obtain a worked product chip of a desired resistance, and cutting width adjusting means 26, 27 for making an adjustment so that the strip 14 is to be cut transversely in the width obtained from the calculating part.
摘要翻译：本发明的目的是提供一种通过简单的工艺制造具有相对较低电阻的金属板片式电阻器的方法和装置，其具有高精度和高产率。该目的是通过用于制造金属板片式电阻器的装置10实现的，包括用于横向切割中间产品条带14的切割模具21，以获得加工产品芯片16a，用于测量加工产品芯片16a的电阻的欧姆计22，具有使用由欧姆计22测量的电阻进行计算的计算部分，以计算要横向切割条带14的宽度，以获得期望电阻的加工产品芯片;以及切割宽度调节装置26， 27，用于进行调整，使得条带14在从计算部分获得的宽度上横向切割。

5. 发明授权

US08584783B2 Motorcycle with supercharger 有权
标题翻译：带增压器的摩托车
公开(公告)号：US08584783B2
公开(公告)日：2013-11-19
申请号：US13531361
申请日：2012-06-22
申请人： Daisuke Saeki , Kazuo Tanaka
发明人： Daisuke Saeki , Kazuo Tanaka
IPC分类号： B62M27/02
CPC分类号： B62M7/02 , B62K19/30 , F02B33/32 , F02M35/162
摘要： A motorcycle includes a combustion engine (E) of a type, in which a cylinder block (34) protrudes upwardly from a crankcase (32), an air cleaner unit (42) for substantially purifying an air, and a supercharger (44) for taking a substantially purified air from the air cleaner unit (42) thereinto and supplying the air towards the combustion engine (E). The supercharger (44) is disposed rearwardly of the cylinder block (34) and the air cleaner unit (42) is disposed rearwardly thereof. Also, a surge tank (48) is disposed rearwardly upwardly of the cylinder block (34) of the combustion engine (E) and above the supercharger (44).
摘要翻译：摩托车包括一种内燃机（E），其中气缸体（34）从曲轴箱（32）向上突出，用于基本上净化空气的空气滤清器单元（42），以及增压器（44），用于从空气滤清器单元（42）中取出基本上净化的空气并将空气供给到内燃机（E）。增压器（44）设置在气缸体（34）的后方，空气滤清器单元（42）设置在气缸体的后方。此外，缓冲罐（48）设置在内燃机（E）的气缸体（34）的上方的上方并且位于增压器（44）的上方。

6. 发明申请

US20130049864A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20130049864A1
公开(公告)日：2013-02-28
申请号：US13589369
申请日：2012-08-20
申请人： Natsuki IKEHATA , Kazuo Tanaka , Takeo Toba , Masashi Arakawa
发明人： Natsuki IKEHATA , Kazuo Tanaka , Takeo Toba , Masashi Arakawa
IPC分类号： H03F3/45
CPC分类号： G11C11/4091 , G11C7/10 , G11C7/1057 , G11C7/1072 , G11C7/1084 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
摘要翻译：差分放大电路的输出信号特性得到改善。当输入数据信号为低电平时，流过第一晶体管的电流将减小，并且第一电阻器和第二电阻器之间的连接（节点）的电位将增加。该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。当输入数据信号为高电平时，第一晶体管的电流增加，因此节点处的电位降低。因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

7. 发明授权

US08173806B2 Method for production of quinazolin-4-one derivative 失效
标题翻译：喹唑啉-4-酮衍生物的制备方法
公开(公告)号：US08173806B2
公开(公告)日：2012-05-08
申请号：US12282381
申请日：2007-03-14
申请人： Kazuo Tanaka , Yoshifumi Sato , Takafumi Yoshimura
发明人： Kazuo Tanaka , Yoshifumi Sato , Takafumi Yoshimura
IPC分类号： C07D239/72
CPC分类号： C07D239/88
摘要： In reacting an anthranilic acid derivative represented by the general formula (1), especially the anthranilic acid derivative selected from anthranilic acid, anthranilamide and anthranilate, with formamide, the reaction is attained under the condition of coexistence of acetic acid and a base as a catalyst in the reaction liquid, and it has made it possible to produce a quinazolin-4-one derivative represented by the general formula (2) and useful as a material for medicine intermediates, at high yield with no side production.
摘要翻译：在使通式（1）表示的邻氨基苯甲酸衍生物，特别是选自邻氨基苯甲酸，邻氨基苯甲酰胺和邻氨基苯甲酸酯的邻氨基苯甲酸衍生物与甲酰胺反应时，在乙酸和碱作为催化剂共存的条件下反应在反应液中，可以以高产率生产无副产物的由通式（2）表示的喹唑啉-4-酮衍生物作为医药中间体的材料。

8. 发明授权

US08139332B2 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit 有权
标题翻译：电平转换电路和采用电平转换电路的半导体集成电路器件
公开(公告)号：US08139332B2
公开(公告)日：2012-03-20
申请号：US13095480
申请日：2011-04-27
申请人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
发明人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
IPC分类号： H02H3/20 , H01L23/60
CPC分类号： H03K3/356113 , H01L2924/0002 , H03K3/356104 , H01L2924/00
摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
摘要翻译：在安装在使用多个高压和低压电源的集成电路装置中的电平转换电路中，提供到差分输入的输入。在降压电路中，栅极和漏极之间以及栅极和源极之间未提供3.3 V的MOS晶体管使用薄的氧化物层。在升高电路中，提供逻辑运算功能。

9. 发明申请

US20110271066A1 STORAGE SYSTEM AND DATA MANAGEMENT METHOD 有权
标题翻译：存储系统和数据管理方法
公开(公告)号：US20110271066A1
公开(公告)日：2011-11-03
申请号：US13179403
申请日：2011-07-08
申请人： Tatsuya NINOMIYA , Kazuo Tanaka
发明人： Tatsuya NINOMIYA , Kazuo Tanaka
IPC分类号： G06F12/00
CPC分类号： G06F12/0868 , G06F12/0811 , G06F2212/284
摘要： The present invention comprises a CHA 110 which transmits/receives data to/from an external device, a DKA 140 which transmits/receives data to/from an HDD unit 200, a primary cache unit 120 which has a primary cache memory 124, a secondary cache unit 130 which is installed between the primary cache unit 120 and the DKA 140 and has a secondary cache memory 134, a CCP 121 which stores write target data received by the CHA 110 in the primary cache memory 124, and a CCP 131 which stores the write target data in the secondary cache memory 134, and transfers the write target data stored in the secondary cache memory 134 to the DKA 140.
摘要翻译：本发明包括向外部设备发送/接收数据的CHA 110，从HDD单元200发送/接收数据的DKA140，具有主高速缓存存储器124的主高速缓存单元120，辅助缓存单元120 高速缓存单元130安装在主缓存单元120和DKA 140之间，并且具有二级高速缓存存储器134，存储由CHA 110接收的写目标数据在一级高速缓冲存储器124中的CCP 121和存储在二次高速缓存存储器134中的写入目标数据，并将存储在二次高速缓冲存储器134中的写入目标数据传送到DKA 140。

10. 发明授权

US08013656B2 Semicondutor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08013656B2
公开(公告)日：2011-09-06
申请号：US12944898
申请日：2010-11-12
申请人： Yusuko Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
发明人： Yusuko Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H01L27/0928 , H01L27/105 , H03K3/356113
摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
摘要翻译：提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元用于驱动主要大型缓冲区。鉴于此，高电压被施加到电平转换器和预缓冲器电路。通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

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