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1. 发明申请

US20130049864A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20130049864A1
公开(公告)日：2013-02-28
申请号：US13589369
申请日：2012-08-20
申请人： Natsuki IKEHATA , Kazuo Tanaka , Takeo Toba , Masashi Arakawa
发明人： Natsuki IKEHATA , Kazuo Tanaka , Takeo Toba , Masashi Arakawa
IPC分类号： H03F3/45
CPC分类号： G11C11/4091 , G11C7/10 , G11C7/1057 , G11C7/1072 , G11C7/1084 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
摘要翻译：差分放大电路的输出信号特性得到改善。当输入数据信号为低电平时，流过第一晶体管的电流将减小，并且第一电阻器和第二电阻器之间的连接（节点）的电位将增加。该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。当输入数据信号为高电平时，第一晶体管的电流增加，因此节点处的电位降低。因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

2. 发明授权

US08803610B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08803610B2
公开(公告)日：2014-08-12
申请号：US13589369
申请日：2012-08-20
申请人： Natsuki Ikehata , Kazuo Tanaka , Takeo Toba , Masashi Arakawa
发明人： Natsuki Ikehata , Kazuo Tanaka , Takeo Toba , Masashi Arakawa
IPC分类号： H03F3/45
CPC分类号： G11C11/4091 , G11C7/10 , G11C7/1057 , G11C7/1072 , G11C7/1084 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.
摘要翻译：差分放大电路的输出信号特性得到改善。当输入数据信号为“低”时，流过第一晶体管的电流将减小，并且第一电阻和第二电阻之间的连接（节点）的电位将增加。该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。当输入数据信号为“高”时，第一晶体管的电流增加，因此节点处的电位减小。因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

3. 发明申请

US20070019493A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20070019493A1
公开(公告)日：2007-01-25
申请号：US11452238
申请日：2006-06-14
申请人： Takeo Toba , Kazuo Tanaka , Shunsuke Toyoshima
发明人： Takeo Toba , Kazuo Tanaka , Shunsuke Toyoshima
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/1066 , G11C11/4074
摘要： The present invention provides a semiconductor integrated circuit having two kinds of input/output circuits realizing higher speed and higher packing density with rational configuration. The semiconductor integrated circuit has a first input/output circuit operating on a first power source voltage, an internal circuit operating on a second power source voltage lower than the first power source voltage, and a second input/output circuit operating on a third power source voltage lower than the first power source voltage. In an output circuit of the first input/output circuit, signal amplitude corresponding to the second power source voltage is converted to signal amplitude corresponding to the first power source voltage by a level shifter, and a P-channel MOSFET and an N-channel MOSFET constructing the output circuit are driven. In an output circuit of the second input/output circuit, a drive signal is generated by a level shifter in a manner similar to the above to drive second and third N-channel MOSFETs for generating an output signal having signal amplitude corresponding to the third power source voltage.
摘要翻译：本发明提供一种具有两种输入/输出电路的半导体集成电路，其实现了具有合理配置的更高速度和更高的封装密度。半导体集成电路具有以第一电源电压工作的第一输入/输出电路，以及低于第一电源电压的第二电源电压运行的内部电路，以及在第三电源上运行的第二输入/输出电路电压低于第一电源电压。在第一输入/输出电路的输出电路中，对应于第二电源电压的信号幅度由电平移位器转换成对应于第一电源电压的信号幅度，以及P沟道MOSFET和N沟道MOSFET 驱动输出电路的构造。在第二输入/输出电路的输出电路中，以与上述类似的方式由电平转换器产生驱动信号，以驱动第二和第三N沟道MOSFET，以产生具有对应于第三功率的信号幅度的输出信号源电压。

4. 发明申请

US20090195292A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20090195292A1
公开(公告)日：2009-08-06
申请号：US12422712
申请日：2009-04-13
申请人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
发明人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H01L27/0928 , H01L27/105 , H03K3/356113
摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
摘要翻译：提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元用于驱动主要大型缓冲区。鉴于此，高电压被施加到电平转换器和预缓冲器电路。通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

5. 发明授权

US07425845B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07425845B2
公开(公告)日：2008-09-16
申请号：US11452238
申请日：2006-06-14
申请人： Takeo Toba , Kazuo Tanaka , Shunsuke Toyoshima
发明人： Takeo Toba , Kazuo Tanaka , Shunsuke Toyoshima
IPC分类号： H03K19/0185
CPC分类号： G11C5/147 , G11C7/1066 , G11C11/4074
摘要： The present invention provides a semiconductor integrated circuit having two kinds of input/output circuits realizing higher speed and higher packing density with rational configuration. The semiconductor integrated circuit has a first input/output circuit operating on a first power source voltage, an internal circuit operating on a second power source voltage lower than the first power source voltage, and a second input/output circuit operating on a third power source voltage lower than the first power source voltage. In an output circuit of the first input/output circuit, signal amplitude corresponding to the second power source voltage is converted to signal amplitude corresponding to the first power source voltage by a level shifter, and a P-channel MOSFET and an N-channel MOSFET constructing the output circuit are driven. In an output circuit of the second input/output circuit, a drive signal is generated by a level shifter in a manner similar to the above to drive second and third N-channel MOSFETs for generating an output signal having signal amplitude corresponding to the third power source voltage.
摘要翻译：本发明提供一种具有两种输入/输出电路的半导体集成电路，其实现了具有合理配置的更高速度和更高的封装密度。半导体集成电路具有以第一电源电压工作的第一输入/输出电路，以及低于第一电源电压的第二电源电压运行的内部电路，以及在第三电源上运行的第二输入/输出电路电压低于第一电源电压。在第一输入/输出电路的输出电路中，对应于第二电源电压的信号幅度由电平移位器转换成对应于第一电源电压的信号幅度，以及P沟道MOSFET和N沟道MOSFET 驱动输出电路的构造。在第二输入/输出电路的输出电路中，以与上述类似的方式由电平转换器产生驱动信号，以驱动第二和第三N沟道MOSFET，以产生具有对应于第三功率的信号幅度的输出信号源电压。

6. 发明授权

US08013656B2 Semicondutor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08013656B2
公开(公告)日：2011-09-06
申请号：US12944898
申请日：2010-11-12
申请人： Yusuko Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
发明人： Yusuko Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H01L27/0928 , H01L27/105 , H03K3/356113
摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
摘要翻译：提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元用于驱动主要大型缓冲区。鉴于此，高电压被施加到电平转换器和预缓冲器电路。通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

7. 发明申请

US20060232307A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20060232307A1
公开(公告)日：2006-10-19
申请号：US11405541
申请日：2006-04-18
申请人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
发明人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
IPC分类号： H03B1/00
CPC分类号： H03K19/018521 , H01L27/0928 , H01L27/105 , H03K3/356113
摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
摘要翻译：提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元用于驱动主要大型缓冲区。鉴于此，高电压被施加到电平转换器和预缓冲器电路。通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

8. 发明授权

US07855590B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07855590B2
公开(公告)日：2010-12-21
申请号：US12422712
申请日：2009-04-13
申请人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
发明人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H01L27/0928 , H01L27/105 , H03K3/356113
摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
摘要翻译：提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元用于驱动主要大型缓冲区。鉴于此，高电压被施加到电平转换器和预缓冲器电路。通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

9. 发明申请

US20100155845A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：US20100155845A1
公开(公告)日：2010-06-24
申请号：US12642760
申请日：2009-12-18
申请人： Takeo Toba , Kazuo Tanaka , Hiroyasu Ishizuka
发明人： Takeo Toba , Kazuo Tanaka , Hiroyasu Ishizuka
IPC分类号： H01L27/06
CPC分类号： H01L27/0292 , H01L24/06 , H01L27/0207 , H01L27/0251 , H01L27/11898 , H01L2224/05553 , H01L2224/06 , H01L2924/1301 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.
摘要翻译：一种具有“I / O单元上的PAD”结构的半导体集成电路器件，其中焊盘引线部分几乎位于I / O部分的中心，以便减小芯片布局面积。在I / O部分中，晶体管最靠近半导体芯片的外围。当在I / O部分的平面图中看到时，电阻位于晶体管的上方，并且第一和第二二极管位于电阻之上; 第二晶体管位于二极管之上; 并且逻辑块位于第二晶体管的上方，其间具有形成在金属布线层中的焊盘引线部分。这允许通过第二晶体管的焊盘在相同的节点上，因此焊盘引线部分可以几乎位于I / O部分的中心。

10. 发明授权

US07532054B2 Semiconductor integrated circuit device having I/O circuitry for low voltage operation 有权
标题翻译：具有用于低压操作的I / O电路的半导体集成电路器件
公开(公告)号：US07532054B2
公开(公告)日：2009-05-12
申请号：US11405541
申请日：2006-04-18
申请人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
发明人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H01L27/0928 , H01L27/105 , H03K3/356113
摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
摘要翻译：提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元用于驱动主要大型缓冲区。鉴于此，高电压被施加到电平转换器和预缓冲器电路。通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

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