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1. 发明授权

US6033971A Semiconductor device having an element isolating oxide film and method of manufacturing the same 有权
标题翻译：具有元件隔离氧化物膜的半导体器件及其制造方法
公开(公告)号：US6033971A
公开(公告)日：2000-03-07
申请号：US160379
申请日：1998-09-25
申请人： Kaoru Motonami , Shigeru Shiratake , Hiroshi Matsuo , Yuichi Yokoyama , Kenji Morisawa , Ritsuko Gotoda , Takaaki Murakami , Satoshi Hamamoto , Kenji Yasumura , Yasuyoshi Itoh
发明人： Kaoru Motonami , Shigeru Shiratake , Hiroshi Matsuo , Yuichi Yokoyama , Kenji Morisawa , Ritsuko Gotoda , Takaaki Murakami , Satoshi Hamamoto , Kenji Yasumura , Yasuyoshi Itoh
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/8234
CPC分类号： H01L21/823475 , H01L21/76205 , H01L21/7621 , H01L21/76216
摘要： There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.
摘要翻译：提供了一种半导体器件，其包括具有良好的上部平坦度的元件隔离氧化物膜及其制造方法。假设tG表示栅电极层6的厚度，从栅极绝缘膜5的上表面到元件隔离氧化膜4的最厚部分的上表面的高度tU和在上表面之间限定的锐角θi 元件隔离氧化膜4和栅极绝缘膜的表面被设置在由公式{θi，tU + 5443 0 = 0.82tG}表示的范围内。因此，未蚀刻部分不保留在用于图形化稍后形成的栅极电极层的蚀刻步骤。这防止了栅电极的短路。由于元件隔离氧化物膜具有改善的平坦度，所以在图案化栅极电极的步骤中可以减少活性区域中的过蚀刻量。这防止了栅极绝缘膜和下面的衬底表面的剃刮。

2. 发明授权

US5831323A Semiconductor device having an element isolating oxide film and method of manufacturing the same 失效
公开(公告)号：US5831323A
公开(公告)日：1998-11-03
申请号：US601662
申请日：1996-02-14
申请人： Kaoru Motonami , Shigeru Shiratake , Hiroshi Matsuo , Yuichi Yokoyama , Kenji Morisawa , Ritsuko Gotoda , Takaaki Murakami , Satoshi Hamamoto , Kenji Yasumura , Yasuyoshi Itoh
发明人： Kaoru Motonami , Shigeru Shiratake , Hiroshi Matsuo , Yuichi Yokoyama , Kenji Morisawa , Ritsuko Gotoda , Takaaki Murakami , Satoshi Hamamoto , Kenji Yasumura , Yasuyoshi Itoh
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L29/00
CPC分类号： H01L21/823475 , H01L21/76205 , H01L21/7621 , H01L21/76216
摘要： There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.

3. 发明授权

US5801427A Semiconductor device having a polycide structure 失效
标题翻译：具有多晶硅结构的半导体器件
公开(公告)号：US5801427A
公开(公告)日：1998-09-01
申请号：US873027
申请日：1997-06-11
申请人： Shigeru Shiratake , Kaoru Motonami , Satoshi Hamamoto
发明人： Shigeru Shiratake , Kaoru Motonami , Satoshi Hamamoto
IPC分类号： H01L21/027 , H01L21/28 , H01L21/336 , H01L21/768 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/94 , H01L31/062
CPC分类号： H01L29/42376 , H01L21/0276 , H01L21/28123 , H01L21/76889 , H01L29/4933 , H01L29/6659 , H01L29/7833
摘要： In a semiconductor device having a polycide structure located on a stepped portion, halation during formation of a resist pattern is prevented, and oxidation of an upper surface of a high-melting-point metal silicide layer is prevented during formation of an interlayer insulating film on the polycide structure. In this semiconductor device, an upper layer which is formed of one layer selected from the group consisting of an amorphous silicon layer, a polycrystalline silicon layer, a TiN layer and a TiW layer is formed on the high-melting-point metal silicide layer forming the polycide structure. This effectively suppresses reflection of light beams by the upper layer located at the stepped portion during exposure for forming the resist pattern on the upper layer. Thereby, formation of a notch at the resist pattern is prevented, and the resist pattern is accurately formed to have a designed pattern. The upper layer made of the amorphous silicon layer or polycrystalline silicon layer prevents formation of an oxide layer at an upper surface of the high-melting-point metal silicide layer due to oxydation by Oxygen carried to the inside of the CVD furnace from the outside during formation of an interlayer insulating film covering the polycide structure.
摘要翻译：在具有位于阶梯部分上的多晶硅结构的半导体器件中，防止形成抗蚀剂图案期间的卤化，并且在层间绝缘膜形成期间防止高熔点金属硅化物层的上表面的氧化多晶硅结构。在该半导体器件中，在高熔点金属硅化物层形成中形成由选自非晶硅层，多晶硅层，TiN层和TiW层的一层形成的上层多晶硅结构。这在上层形成抗蚀剂图案的曝光期间有效地抑制位于台阶部分的上层的光束的反射。由此，防止在抗蚀剂图案处形成切口，并且将抗蚀剂图形精确地形成为具有设计图案。由非晶硅层或多晶硅层制成的上层防止在高熔点金属硅化物层的上表面形成氧化物层，这是由于氧化从CVD外部向内部送入CVD炉内形成覆盖多晶硅化物结构的层间绝缘膜。

4. 发明申请

US20080135909A1 DISPLAY DEVICE AND METHOD OF PRODUCING THE SAME 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20080135909A1
公开(公告)日：2008-06-12
申请号：US11948377
申请日：2007-11-30
申请人： Toru Takeguchi , Takuji Imamura , Kazushi Yamayoshi , Tomoyuki Irizumi , Atsunori Nishiura , Kaoru Motonami
发明人： Toru Takeguchi , Takuji Imamura , Kazushi Yamayoshi , Tomoyuki Irizumi , Atsunori Nishiura , Kaoru Motonami
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L28/60 , G02F1/136213 , G02F1/136227 , H01L27/1255 , H01L27/1288
摘要： In a thin film transistor using a polycrystalline semiconductor film, when a storage capacitor is formed, it is often that a polycrystalline semiconductor film is used also in one electrode of the capacity. In a display device having a storage capacitor and thin film transistor which have a polycrystalline semiconductor film, the storage capacitor exhibits a voltage dependency due to the semiconductor film, and hence a display failure is caused. In the display device of the invention, a metal conductive film 5 is stacked above a semiconductor layer 4d made of a polycrystalline semiconductor film which is used as a lower electrode of a storage capacitor 130.
摘要翻译：在使用多晶半导体膜的薄膜晶体管中，当形成存储电容时，通常多晶半导体膜也用于一个容量的电极中。在具有具有多晶半导体膜的存储电容器和薄膜晶体管的显示装置中，存储电容器由于半导体膜而呈现电压依赖性，因此导致显示不良。在本发明的显示装置中，金属导电膜5层叠在用作保持电容器130的下电极的多晶半导体膜的半导体层4d的上方。

5. 发明申请

US20070200111A1 IMAGE DISPLAY DEVICE 有权
标题翻译：图像显示设备
公开(公告)号：US20070200111A1
公开(公告)日：2007-08-30
申请号：US11624419
申请日：2007-01-18
申请人： Yasuyoshi Itoh , Kaoru Motonami
发明人： Yasuyoshi Itoh , Kaoru Motonami
IPC分类号： H01L29/04
CPC分类号： G02F1/133553 , G02F1/133345 , G02F1/13454 , G02F1/136286 , G02F2001/136231
摘要： An additional circuit is formed on a glass substrate, and a passivation film is deposited thereon. After an insulation film is deposited on the passivation film, a contact hole is formed, and a signal line is deposited and connected to the additional circuit. After the signal line and the insulation film are patterned, an organic insulation film is formed, to thereby have a surface of an uneven configuration depending on a step formed by the signal line and the insulation film. A reflective electrode is formed on the organic insulation film, to thereby have a surface of an uneven configuration. This eliminates the need to perform a photolithography process step for the formation of the surface of the organic insulation film in the uneven configuration, thereby reducing manufacturing costs.
摘要翻译：在玻璃基板上形成附加电路，并在其上沉积钝化膜。在绝缘膜沉积在钝化膜上之后，形成接触孔，并且将信号线沉积并连接到附加电路。在信号线和绝缘膜被图案化之后，形成有机绝缘膜，从而具有取决于由信号线和绝缘膜形成的台阶的不平坦构造的表面。反射电极形成在有机绝缘膜上，从而具有凹凸形状的表面。因此，不需要进行用于形成不均匀构造的有机绝缘膜的表面的光刻工序，从而降低制造成本。

6. 发明授权

US5962907A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5962907A
公开(公告)日：1999-10-05
申请号：US967614
申请日：1997-11-10
申请人： Kaoru Motonami
发明人： Kaoru Motonami
IPC分类号： H01L21/8234 , H01L21/82 , H01L21/8239 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/105 , H01L29/00 , H01L27/108
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/1052
摘要： A semiconductor device having a memory device and a logic device formed together on a single chip is provided. A first element region and a second element region of a semiconductor substrate are formed spaced apart from each other with an isolation region therebetween. A floating conductive film is provided on the isolation region.
摘要翻译：提供了具有在单个芯片上一起形成的存储器件和逻辑器件的半导体器件。半导体衬底的第一元件区域和第二元件区域之间具有隔离区域形成为彼此间隔开。在隔离区域上设置浮置导电膜。

7. 发明授权

US5280444A Dram comprising stacked-type capacitor having vertically protruding part and method of manufacturing the same 失效
标题翻译： Dram包括具有垂直突出部分的堆叠型电容器及其制造方法
公开(公告)号：US5280444A
公开(公告)日：1994-01-18
申请号：US851409
申请日：1992-03-13
申请人： Kaoru Motonami , Yoshinori Okumura
发明人： Kaoru Motonami , Yoshinori Okumura
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00 , G11C11/24
CPC分类号： H01L27/10817
摘要： A storage node of a stacked capacitor in a DRAM comprises a first part connected to a source/drain region and a second part protruding upward from a substrate in a vertical wall shape. The second part includes a concave part in the inner part which is removed by etching. Steps are formed on the inner and outer peripheral surfaces of the vertical wall part. The steps are formed by a self-alignment method using a sidewall insulating layer formed by anisotropic etching. Capacitance of the capacitor is increased by forming steps on the surface of the storage node.
摘要翻译： DRAM中层叠电容器的存储节点包括连接到源极/漏极区域的第一部分和从垂直壁形状的基板向上突出的第二部分。第二部分包括通过蚀刻去除的内部部分中的凹部。在垂直壁部的内周面和外周面上形成台阶。该步骤通过使用由各向异性蚀刻形成的侧壁绝缘层的自对准方法形成。通过在存储节点的表面上形成步骤来增加电容器的电容。

8. 发明授权

US5240872A Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions 失效
标题翻译：制造具有接触源极/漏极区域的互连层的半导体器件的方法
公开(公告)号：US5240872A
公开(公告)日：1993-08-31
申请号：US925148
申请日：1992-08-06
申请人： Kaoru Motonami , Natsuo Ajika , Atsushi Hachisuka , Yoshinori Okumura , Yasushi Matsui
发明人： Kaoru Motonami , Natsuo Ajika , Atsushi Hachisuka , Yoshinori Okumura , Yasushi Matsui
IPC分类号： H01L21/8242 , H01L23/485 , H01L27/108
CPC分类号： H01L27/10873 , H01L23/485 , H01L27/10817 , H01L2924/0002
摘要： A semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.
摘要翻译：半导体器件包括MOS型场效应晶体管，其栅极（4）的表面被第一绝缘膜（5）覆盖，左右侧设置有一对第二绝缘膜（10）。第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面（4）。至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

9. 发明授权

US5218219A Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region 失效
标题翻译：在存储器单元区域和外围电路区域的边界区域具有外围壁的半导体存储器件
公开(公告)号：US5218219A
公开(公告)日：1993-06-08
申请号：US678872
申请日：1991-04-04
申请人： Natsuo Ajika , Hideaki Arima , Kaoru Motonami , Atsushi Hachisuka , Tomonori Okudaira
发明人： Natsuo Ajika , Hideaki Arima , Kaoru Motonami , Atsushi Hachisuka , Tomonori Okudaira
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10817
摘要： A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.
摘要翻译：公开了一种动态随机存取存储器（DRAM），其即使在高集成器件中也能够有效地防止存储单元阵列101和外围电路102的边界区域中的步骤的形成。该DRAM包括在存储单元阵列101的边界区域和P型硅衬底1的外围电路102的外围壁20a和20b的双周壁20，P型硅衬底1从P型硅衬底1垂直向上延伸。形成在存储单元阵列上的器件的表面和外围电路102在存储单元阵列101和外围电路102上的形成装置中通过双周壁20的病毒基本平坦化，从而有效地防止了在步骤存储单元阵列101和外围电路102的边界区域，即使在高集成器件中。

10. 发明授权

US08435417B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08435417B2
公开(公告)日：2013-05-07
申请号：US12827259
申请日：2010-06-30
申请人： Kazunari Nakata , Kaoru Motonami , Atsushi Narazaki , Ayumu Onoyama , Shigeto Honda , Ryoichi Fujii , Tomoya Hirata
发明人： Kazunari Nakata , Kaoru Motonami , Atsushi Narazaki , Ayumu Onoyama , Shigeto Honda , Ryoichi Fujii , Tomoya Hirata
IPC分类号： B44C1/22
CPC分类号： H01L21/3083 , H01L21/304 , H01L21/6835 , H01L21/6836 , H01L2221/68327 , H01L2221/6834 , H01L2924/0002 , H01L2924/30105 , H01L2924/00
摘要： A passivation film having a predetermined width from an outer peripheral end portion toward an inner side and extending along the outer peripheral end portion is formed on a front surface of a semiconductor substrate. An outer peripheral end surface orthogonal to the front surface and a rear surface is formed by grinding the outer peripheral end portion of the semiconductor substrate. A thickness of the semiconductor substrate is reduced to a predetermined thickness by grinding the rear surface. The ground rear surface is etched by discharging a mixed acid onto the rear surface while rotating the semiconductor substrate with the rear surface facing upward, to remove a fracture layer. Thereby, chipping or cracking of the semiconductor substrate is suppressed.
摘要翻译：在半导体衬底的前表面上形成有从外周端向内侧具有预定宽度且沿外周端部延伸的钝化膜。通过研磨半导体衬底的外周端部形成与前表面和后表面正交的外周端面。通过研磨后表面将半导体衬底的厚度减小到预定厚度。通过将混合酸排放到后表面上同时使后表面朝上的半导体衬底旋转来蚀刻地面后表面，以除去断裂层。由此，能够抑制半导体基板的切削或破裂。

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