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1. 发明申请

US20120205756A1 SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME 有权
标题翻译：半导体器件及其测试方法
公开(公告)号：US20120205756A1
公开(公告)日：2012-08-16
申请号：US13272512
申请日：2011-10-13
申请人： Atsushi NARAZAKI
发明人： Atsushi NARAZAKI
IPC分类号： H01L29/84 , H01L21/66
CPC分类号： H01L22/14 , G01L1/18 , G01L5/0047 , G01R31/2884 , H01L22/12 , H01L23/3121 , H01L24/32 , H01L24/73 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/014 , H01L2924/1203 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00012 , H01L2924/3512 , H01L2924/00
摘要： A semiconductor device includes a semiconductor chip with a gate electrode, and a stress detecting element placed on a surface of the semiconductor chip, and which detects stress applied to the surface. The semiconductor device controls a control signal to be applied to the gate electrode in response to stress detected by the stress detecting element. The stress detecting element is preferably provided as a first stress detecting element which detects stress applied to a central portion of the semiconductor chip in plan view. The stress detecting element is preferably provided as a second stress detecting element which detects stress applied to a circumferential portion of the semiconductor chip in plan view.
摘要翻译：半导体器件包括具有栅电极的半导体芯片和放置在半导体芯片的表面上的应力检测元件，并且检测施加到表面的应力。半导体器件响应于由应力检测元件检测到的应力来控制施加到栅电极的控制信号。应力检测元件优选地设置为在平面图中检测施加到半导体芯片的中心部分的应力的第一应力检测元件。应力检测元件优选地设置为在平面图中检测施加到半导体芯片的圆周部分的应力的第二应力检测元件。

2. 发明申请

US20100240183A1 METHOD OF MANUFACTURING POWER SEMICONDUCTOR DEVICE 有权
标题翻译：制造功率半导体器件的方法
公开(公告)号：US20100240183A1
公开(公告)日：2010-09-23
申请号：US12558999
申请日：2009-09-14
申请人： Atsushi NARAZAKI
发明人： Atsushi NARAZAKI
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/66348 , H01L29/66719 , H01L29/66734 , H01L29/7397
摘要： A mask layer having a plurality of openings is formed on the first layer. A second layer having a second conductivity type different from the first conductivity type is formed on the first layer by introducing impurities using the mask layer. A third layer having the first conductivity type is formed on the second layer by introducing impurities using the mask layer. A trench extending through the second layer and the third layer to the first layer is formed by carrying out etching using an etching mask including at least the mask layer. A gate insulation film covering a sidewall of the trench is formed. A trench gate filling the trench is formed on the gate insulation film.
摘要翻译：在第一层上形成具有多个开口的掩模层。通过使用掩模层引入杂质，在第一层上形成具有不同于第一导电类型的第二导电类型的第二层。通过使用掩模层引入杂质，在第二层上形成具有第一导电类型的第三层。通过使用至少包括掩模层的蚀刻掩模进行蚀刻来形成延伸穿过第二层和第三层到第一层的沟槽。形成覆盖沟槽侧壁的栅极绝缘膜。填充沟槽的沟槽栅极形成在栅极绝缘膜上。

3. 发明申请

US20090072268A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090072268A1
公开(公告)日：2009-03-19
申请号：US12020959
申请日：2008-01-28
申请人： Kenji Hatori , Atsushi Narazaki
发明人： Kenji Hatori , Atsushi Narazaki
IPC分类号： H01L29/739 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0834 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66333 , H01L29/7395 , H01L29/7816
摘要： A semiconductor device includes a semiconductor substrate having a main surface and a semiconductor element having an insulated gate field effect portion formed in the semiconductor substrate. The semiconductor element includes an n− region, an n-type source region, a p-type base region, an n+ region, and a gate electrode. The n− region and the n-type source region are formed in the main surface. The p-type base region is formed in the main surface adjacent to the n-type source region. The n+ region is formed in the main surface adjacent to the p-type base region and opposed to the n-type source region with the p-type base region being interposed, and has an impurity concentration higher than the n− region. The n− region is formed in the main surface adjacent to the p-type base region and to the n+ region.
摘要翻译：半导体器件包括具有主表面的半导体衬底和形成在半导体衬底中的具有绝缘栅场效应部分的半导体元件。半导体元件包括n区，n型源极区，p型基极区域，n +区域和栅电极。在主表面上形成n区和n型源极区。 p型基极区域形成在与n型源极区域相邻的主表面上。在与p型基极区相邻的主表面上形成n +区，与插入有p型基极区的n型源极区相比，具有比n区高的杂质浓度。 n区形成在与p型基区相邻的主表面和n +区中。

4. 发明授权

US06285058B1 Insulated gate semiconductor device and method of manufacturing the same 有权
标题翻译：绝缘栅半导体器件及其制造方法
公开(公告)号：US06285058B1
公开(公告)日：2001-09-04
申请号：US09485702
申请日：2000-02-28
申请人： Atsushi Narazaki , Hidetoshi Souno , Yasunori Yamashita
发明人： Atsushi Narazaki , Hidetoshi Souno , Yasunori Yamashita
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/4232 , H01L29/4238
摘要： The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to an improvement for enhancing a gate breakdown voltage. In order to achieve the object, gate wirings (9), (10) and (13) are provided to keep away from an upper end (UE) of an edge of a gate trench (6) along its longitudinal direction. More specifically, the gate wiring (9) coupled integrally with an upper surface of a gate electrode (7) is formed apart from the upper end (UE) and the gate wiring (10) is formed on an insulating film (4) also apart from the upper end (UE). The two gate wirings (9) and (10) are connected to each other through the gate wiring (13) formed on a BPSG layer (11). Moreover, an upper face of the gate electrode (7) is positioned on the same level as an upper main surface of a semiconductor substrate (90) or therebelow in the vicinity of the upper end (UE). Consequently, a concentration of an electric field generated in insulating films (8) and (17) covering the upper end (UE) can be relieved or eliminated.
摘要翻译：绝缘栅半导体器件及其制造方法技术领域本发明涉及绝缘栅半导体器件及其制造方法，更具体地，涉及提高栅极击穿电压的改进。为了实现该目的，提供了栅极布线（9），（10）和（13）以沿着其纵向方向远离栅极沟槽（6）的边缘的上端（UE）。更具体地，与栅电极（7）的上表面一体地结合的栅极布线（9）形成为与上端（UE）分开，并且栅极布线（10）也形成在也分开的绝缘膜（4）上来自上端（UE）。两个栅极布线（9）和（10）通过形成在BPSG层（11）上的栅极布线（13）相互连接。此外，栅电极（7）的上表面位于与半导体衬底（90）的上主表面或其上端附近相同的高度。因此，可以减轻或消除在覆盖上端（UE）的绝缘膜（8）和（17）中产生的电场的浓度。

5. 发明授权

US08884383B2 Semiconductor device and method of testing the same 有权
标题翻译：半导体器件及其测试方法
公开(公告)号：US08884383B2
公开(公告)日：2014-11-11
申请号：US13272512
申请日：2011-10-13
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L29/84 , H01L21/66 , G01R31/28 , H01L23/00 , H01L23/31
CPC分类号： H01L22/14 , G01L1/18 , G01L5/0047 , G01R31/2884 , H01L22/12 , H01L23/3121 , H01L24/32 , H01L24/73 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/014 , H01L2924/1203 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00012 , H01L2924/3512 , H01L2924/00
摘要： A semiconductor device includes a semiconductor chip with a gate electrode, and a stress detecting element placed on a surface of the semiconductor chip, and which detects stress applied to the surface. The semiconductor device controls a control signal to be applied to the gate electrode in response to stress detected by the stress detecting element. The stress detecting element is preferably provided as a first stress detecting element which detects stress applied to a central portion of the semiconductor chip in plan view. The stress detecting element is preferably provided as a second stress detecting element which detects stress applied to a circumferential portion of the semiconductor chip in plan view.
摘要翻译：半导体器件包括具有栅电极的半导体芯片和放置在半导体芯片的表面上的应力检测元件，并且检测施加到表面的应力。半导体器件响应于由应力检测元件检测到的应力来控制施加到栅电极的控制信号。应力检测元件优选地设置为在平面图中检测施加到半导体芯片的中心部分的应力的第一应力检测元件。应力检测元件优选地设置为在平面图中检测施加到半导体芯片的圆周部分的应力的第二应力检测元件。

6. 发明授权

US08618604B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08618604B2
公开(公告)日：2013-12-31
申请号：US12848411
申请日：2010-08-02
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L21/0274 , H01L21/3083 , H01L29/0696 , H01L29/4238 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer has a main surface. A main chip region is formed on the main surface. A sub-chip region is smaller in area than the main chip region, and positioned on an edge side of the semiconductor wafer relative to the main chip region. The sub-chip region is identical to the main chip region in design pattern. Accordingly, a semiconductor device in which occurrence of a pattern failure at the edge of the wafer can be prevented when chips are arranged in the surface of the semiconductor wafer and a method of manufacturing the same can be obtained.
摘要翻译：半导体晶片具有主表面。主芯片区域形成在主表面上。子芯片区域的面积小于主芯片区域，并且位于半导体晶片相对于主芯片区域的边缘侧。子芯片区域与设计图案中的主芯片区域相同。因此，当芯片布置在半导体晶片的表面中时，可以防止在晶片边缘发生图案故障的半导体器件及其制造方法。

7. 发明授权

US08519733B2 Method of measuring characteristics of a semiconductor element and method of manufacturing a semiconductor device 有权
标题翻译：测量半导体元件的特性的方法和制造半导体器件的方法
公开(公告)号：US08519733B2
公开(公告)日：2013-08-27
申请号：US13044985
申请日：2011-03-10
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A measurement terminal is arranged at an edge of a semiconductor wafer to be apart from a gate electrode and a source electrode formed in a surface portion on one side in a thickness direction of a semiconductor wafer so that an electrode contact portion is in contact with a drain electrode on the other side in the thickness direction of the semiconductor wafer and that a terminal contact portion is exposed to the one side in the thickness direction of the semiconductor wafer. A probe terminal is brought into contact with the terminal contact portion of the measurement terminal and the probe terminal is brought into contact with the gate electrode and the source electrode, to thereby measure electrical characteristics of a MOSFET.
摘要翻译：测量端子布置在半导体晶片的边缘处，以与半导体晶片的厚度方向上形成在一侧的表面部分中的栅电极和源电极分开，使得电极接触部分与电极接触部分接触在半导体晶片的厚度方向上的另一侧的漏极电极，并且端子接触部分在半导体晶片的厚度方向上暴露于一侧。探针端子与测量端子的端子接触部分接触，并且探针端子与栅电极和源电极接触，从而测量MOSFET的电特性。

8. 发明授权

US08450183B2 Power semiconductor device and method of manufacturing the same 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08450183B2
公开(公告)日：2013-05-28
申请号：US12961905
申请日：2010-12-07
申请人： Ryoichi Fujii , Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
发明人： Ryoichi Fujii , Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
IPC分类号： H01L21/76 , H01L31/0312 , H01L23/58
CPC分类号： H01L29/063 , H01L29/0615 , H01L29/0661 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.
摘要翻译：根据本发明的制造功率半导体器件的方法包括以下步骤：（a）在半导体衬底上形成氮化硅膜; （b）在步骤（a）之后，沿着半导体衬底6的周边部分形成环形沟槽; （c）在所述沟槽的内表面上形成第一氧化硅膜; （d）在步骤（c）之后，在半导体衬底的整个表面上形成第二氧化硅膜以埋置沟槽; （e）通过使用氮化硅膜作为塞子来平坦化第二氧化硅膜; 和（f）在除去氮化硅膜的区域中形成第三氧化硅膜。

9. 发明授权

US08247867B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08247867B2
公开(公告)日：2012-08-21
申请号：US12836922
申请日：2010-07-15
申请人： Kazunari Nakata , Atsushi Narazaki , Shigeto Honda , Kaoru Motonami
发明人： Kazunari Nakata , Atsushi Narazaki , Shigeto Honda , Kaoru Motonami
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a stripe shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 μm or more.
摘要翻译：半导体器件包括具有第一导电类型的基极层，形成在基极层上并具有第二导电类型的源极层，以及形成在源极层上的绝缘膜。半导体器件还包括穿透基底层的多个栅极结构，以及穿透绝缘膜和源极层并将源极层和基极层彼此电连接的多个导电部件。栅极结构在平面图中形成为条状。导电部分连接到基底层的部分在平面图中形成为条形，并且形成在栅极结构之间。此外，栅极结构和导电部之间的源极层和基极层彼此接触的部分的尺寸为0.36μm以上。

10. 发明申请

US20120153382A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120153382A1
公开(公告)日：2012-06-21
申请号：US13205085
申请日：2011-08-08
申请人： Atsushi NARAZAKI , Hisaaki YOSHIDA , Kazuaki HIGASHI
发明人： Atsushi NARAZAKI , Hisaaki YOSHIDA , Kazuaki HIGASHI
IPC分类号： H01L29/78 , B82Y99/00
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/4238 , H01L29/7811
摘要： A semiconductor device includes a trench extending from a surface of a P-base layer to a surface of a P-well layer. The trench has a trench end portion defined in the surface of the P-well layer and in a direction in which the trench extends. The trench has first and second regions. The first region extends from the trench end portion to get into the surface of the P-base layer near a boundary between the P-base layer and the P-well layer. The second region extends in the surface of the P-base layer from an end portion of the first region. A trench width is greater in the first region than in the second region.
摘要翻译：半导体器件包括从P基层的表面延伸到P阱层的表面的沟槽。沟槽具有限定在P阱层的表面中并且在沟槽延伸的方向上的沟槽端部。沟渠有第一和第二区域。第一区域从沟槽末端部延伸到P基层与P阱层之间的边界附近的P基层的表面。第二区域从第一区域的端部在P基层的表面延伸。沟道宽度在第一区域比在第二区域中大。

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