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1. 发明申请

US20080135909A1 DISPLAY DEVICE AND METHOD OF PRODUCING THE SAME 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20080135909A1
公开(公告)日：2008-06-12
申请号：US11948377
申请日：2007-11-30
申请人： Toru Takeguchi , Takuji Imamura , Kazushi Yamayoshi , Tomoyuki Irizumi , Atsunori Nishiura , Kaoru Motonami
发明人： Toru Takeguchi , Takuji Imamura , Kazushi Yamayoshi , Tomoyuki Irizumi , Atsunori Nishiura , Kaoru Motonami
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L28/60 , G02F1/136213 , G02F1/136227 , H01L27/1255 , H01L27/1288
摘要： In a thin film transistor using a polycrystalline semiconductor film, when a storage capacitor is formed, it is often that a polycrystalline semiconductor film is used also in one electrode of the capacity. In a display device having a storage capacitor and thin film transistor which have a polycrystalline semiconductor film, the storage capacitor exhibits a voltage dependency due to the semiconductor film, and hence a display failure is caused. In the display device of the invention, a metal conductive film 5 is stacked above a semiconductor layer 4d made of a polycrystalline semiconductor film which is used as a lower electrode of a storage capacitor 130.
摘要翻译：在使用多晶半导体膜的薄膜晶体管中，当形成存储电容时，通常多晶半导体膜也用于一个容量的电极中。在具有具有多晶半导体膜的存储电容器和薄膜晶体管的显示装置中，存储电容器由于半导体膜而呈现电压依赖性，因此导致显示不良。在本发明的显示装置中，金属导电膜5层叠在用作保持电容器130的下电极的多晶半导体膜的半导体层4d的上方。

2. 发明授权

US07754541B2 Display device and method of producing the same 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US07754541B2
公开(公告)日：2010-07-13
申请号：US11948377
申请日：2007-11-30
申请人： Toru Takeguchi , Takuji Imamura , Kazushi Yamayoshi , Tomoyuki Irizumi , Atsunori Nishiura , Kaoru Motonami
发明人： Toru Takeguchi , Takuji Imamura , Kazushi Yamayoshi , Tomoyuki Irizumi , Atsunori Nishiura , Kaoru Motonami
IPC分类号： H01L21/00
CPC分类号： H01L28/60 , G02F1/136213 , G02F1/136227 , H01L27/1255 , H01L27/1288
摘要： In a thin film transistor using a polycrystalline semiconductor film, when a storage capacitor is formed, it is often that a polycrystalline semiconductor film is used also in one electrode of the capacity. In a display device having a storage capacitor and thin film transistor which have a polycrystalline semiconductor film, the storage capacitor exhibits a voltage dependency due to the semiconductor film, and hence a display failure is caused. In the display device of the invention, a metal conductive film 5 is stacked above a semiconductor layer 4d made of a polycrystalline semiconductor film which is used as a lower electrode of a storage capacitor 130.
摘要翻译：在使用多晶半导体膜的薄膜晶体管中，当形成存储电容时，通常多晶半导体膜也用于一个容量的电极中。在具有具有多晶半导体膜的存储电容器和薄膜晶体管的显示装置中，存储电容器由于半导体膜而呈现电压依赖性，因此导致显示不良。在本发明的显示装置中，金属导电膜5堆叠在用作存储电容器130的下电极的多晶半导体膜制成的半导体层4d的上方。

3. 发明申请

US20080083927A1 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：显示装置及其制造方法
公开(公告)号：US20080083927A1
公开(公告)日：2008-04-10
申请号：US11866132
申请日：2007-10-02
申请人： Atsunori Nishiura , Toru Takeguchi , Takuji Imamura
发明人： Atsunori Nishiura , Toru Takeguchi , Takuji Imamura
IPC分类号： H01L29/04 , H01L21/00
CPC分类号： G02F1/136227 , G02F2001/136231 , H01L27/124 , H01L27/1248 , H01L29/41733
摘要： A display device includes a substrate, a gate insulating film provided over the substrate and disposed between a semiconductor layer and a first conductive layer including a capacitor electrode and a gate electrode, an interlayer insulating film formed over the semiconductor layer, the first conductive layer and the gate insulating film, a second conductive layer having a signal line formed over the interlayer insulating film, a protective film formed over the interlayer insulating film and the second conductive layer and a pixel electrode layer formed over the protective film. The semiconductor layer and the second conductive layer are connected via the pixel electrode layer by the pixel electrode layer penetrating the protective film to reach the second conductive layer and also penetrating the protective film, the interlayer insulating film and the gate insulating film to reach the semiconductor layer.
摘要翻译：一种显示装置，包括：衬底，设置在衬底上并设置在半导体层和包括电容器电极和栅电极的第一导电层之间的栅极绝缘膜，形成在半导体层上的层间绝缘膜，第一导电层和栅绝缘膜，在层间绝缘膜上形成有信号线的第二导电层，形成在层间绝缘膜和第二导电层上的保护膜和形成在保护膜上的像素电极层。半导体层和第二导电层经由像素电极层被穿透保护膜的像素电极层连接到第二导电层，并且还穿透保护膜，层间绝缘膜和栅极绝缘膜以到达半导体层。

4. 发明授权

US07388229B2 Thin film transistor substrate, manufacturing method of thin film transistor, and display device 有权
标题翻译：薄膜晶体管基板，薄膜晶体管的制造方法以及显示装置
公开(公告)号：US07388229B2
公开(公告)日：2008-06-17
申请号：US11782213
申请日：2007-07-24
申请人： Atsunori Nishiura , Takuji Imamura
发明人： Atsunori Nishiura , Takuji Imamura
IPC分类号： H01L27/14
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/1288
摘要： A thin film transistor substrate includes a first conductive layer formed on a substrate, an anti-diffusion layer deposited on the first conductive layer, a semiconductor layer formed on the anti-diffusion layer, a gate insulating layer deposited on the semiconductor layer, a second conductive layer formed on the gate insulating layer, an interlayer insulating layer deposited on the second conductive layer, and a third conductive layer formed on the interlayer insulating layer, in a first contact hole penetrating through the interlayer insulating layer and the gate insulating layer to reach the semiconductor layer, and in a second contact hole penetrating through the interlayer insulating layer, the gate insulating layer and the anti-diffusion layer to reach the first conductive layer. The third conductive layer includes a pixel electrode formed in island shape on the interlayer insulating layer.
摘要翻译：薄膜晶体管基板包括形成在基板上的第一导电层，沉积在第一导电层上的抗扩散层，形成在反扩散层上的半导体层，沉积在半导体层上的栅极绝缘层，第二导电层形成在栅极绝缘层上的导电层，沉积在第二导电层上的层间绝缘层和形成在层间绝缘层上的第三导电层，穿过层间绝缘层和栅绝缘层的第一接触孔到达半导体层，以及穿过层间绝缘层的第二接触孔，栅极绝缘层和抗扩散层，以到达第一导电层。第三导电层包括在层间绝缘层上形成为岛状的像素电极。

5. 发明申请

US20080035930A1 THIN FILM TRANSISTOR SUBSTRATE, MANUFACTURING METHOD OF THIN FILM TRANSISTOR, AND DISPLAY DEVICE 有权
标题翻译：薄膜晶体管基板，薄膜晶体管的制造方法和显示装置
公开(公告)号：US20080035930A1
公开(公告)日：2008-02-14
申请号：US11782213
申请日：2007-07-24
申请人： Atsunori Nishiura , Takuji Imamura
发明人： Atsunori Nishiura , Takuji Imamura
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/1288
摘要： A thin film transistor substrate includes a first conductive layer formed on a substrate, an anti-diffusion layer deposited on the first conductive layer, a semiconductor layer formed on the anti-diffusion layer, a gate insulating layer deposited on the semiconductor layer, a second conductive layer formed on the gate insulating layer, an interlayer insulating layer deposited on the second conductive layer, and a third conductive layer formed on the interlayer insulating layer, in a first contact hole penetrating through the interlayer insulating layer and the gate insulating layer to reach the semiconductor layer, and in a second contact hole penetrating through the interlayer insulating layer, the gate insulating layer and the anti-diffusion layer to reach the first conductive layer. The third conductive layer includes a pixel electrode formed in island shape on the interlayer insulating layer.
摘要翻译：薄膜晶体管基板包括形成在基板上的第一导电层，沉积在第一导电层上的抗扩散层，形成在反扩散层上的半导体层，沉积在半导体层上的栅极绝缘层，第二导电层形成在栅极绝缘层上的导电层，沉积在第二导电层上的层间绝缘层和形成在层间绝缘层上的第三导电层，穿过层间绝缘层和栅极绝缘层的第一接触孔到达半导体层，以及穿过层间绝缘层的第二接触孔，栅极绝缘层和抗扩散层，以到达第一导电层。第三导电层包括在层间绝缘层上形成为岛状的像素电极。

6. 发明申请

US20080017865A1 THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US20080017865A1
公开(公告)日：2008-01-24
申请号：US11765103
申请日：2007-06-19
申请人： Yasuyoshi Itoh , Atsunori Nishiura
发明人： Yasuyoshi Itoh , Atsunori Nishiura
IPC分类号： H01L29/04 , H01L21/8238
CPC分类号： H01L27/12 , H01L29/42384 , H01L29/78612 , H01L29/78696
摘要： A thin film transistor substrate includes a thin film transistor of a first conductivity type, a semiconductor layer having a channel region of the first conductivity type placed between the source/drain regions, a gate electrode formed to an opposite face to the semiconductor layer with an gate insulating film interposed therebetween, an opening in the gate electrode corresponding to both edges in a channel width direction of the channel region. In the channel region corresponding to the opening, a highly concentrated impurity region having a higher impurity concentration of the first conductivity type than the channel corresponding to the gate electrode is formed.
摘要翻译：薄膜晶体管衬底包括第一导电类型的薄膜晶体管，具有位于源极/漏极区之间的具有第一导电类型的沟道区的半导体层，形成在与半导体层相反的面上的栅电极，栅极绝缘膜之间，栅极电极中的开口对应于沟道区域的沟道宽度方向上的两个边缘。在与开口对应的沟道区域中，形成了比与栅电极对应的沟道的第一导电类型的杂质浓度高的高浓度杂质区。

7. 发明授权

US07473972B2 Thin film transistor substrate and method for manufacturing the same 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US07473972B2
公开(公告)日：2009-01-06
申请号：US11765103
申请日：2007-06-19
申请人： Yasuyoshi Itoh , Atsunori Nishiura
发明人： Yasuyoshi Itoh , Atsunori Nishiura
IPC分类号： H01L29/417
CPC分类号： H01L27/12 , H01L29/42384 , H01L29/78612 , H01L29/78696
摘要： A thin film transistor substrate includes a thin film transistor of a first conductivity type, a semiconductor layer having a channel region of the first conductivity type placed between the source/drain regions, a gate electrode formed to an opposite face to the semiconductor layer with an gate insulating film interposed therebetween, an opening in the gate electrode corresponding to both edges in a channel width direction of the channel region. In the channel region corresponding to the opening, a highly concentrated impurity region having a higher impurity concentration of the first conductivity type than the channel corresponding to the gate electrode is formed.
摘要翻译：薄膜晶体管衬底包括第一导电类型的薄膜晶体管，具有位于源极/漏极区之间的具有第一导电类型的沟道区的半导体层，形成在与半导体层相反的面上的栅电极，栅极绝缘膜之间，栅极电极中的开口对应于沟道区域的沟道宽度方向上的两个边缘。在与开口对应的沟道区域中，形成了比与栅电极对应的沟道的第一导电类型的杂质浓度高的高浓度杂质区。

8. 发明授权

US06740598B2 Wiring layer dry etching method and semiconductor device manufacturing method 失效
标题翻译：接线层干式蚀刻法及半导体器件制造方法
公开(公告)号：US06740598B2
公开(公告)日：2004-05-25
申请号：US10118375
申请日：2002-04-09
申请人： Kenji Kawai , Atsunori Nishiura , Ryoichi Yoshifuku
发明人： Kenji Kawai , Atsunori Nishiura , Ryoichi Yoshifuku
IPC分类号： H01L21302
CPC分类号： H01L21/32136 , H01L21/32137
摘要： A wiring layer dry etching method is improved not to reduce electrical characteristics of a semiconductor device. A semiconductor substrate on which a mask for patterning a wiring layer is formed is prepared, in which mask is formed on wiring layer (a first step). Affected layers on a surface of the wiring layer are dry-etched and removed (second step). Wiring layer is dry-etched by using mask (third step). When shifting is performed from the second step to the third step, vacuuming is not performed, and continuous discharge is performed.
摘要翻译：改进了布线层干式蚀刻方法，不会降低半导体器件的电特性。制备其上形成用于图案化布线层的掩模的半导体基板，其中在布线层上形成掩模（第一步骤）。干式蚀刻并去除了布线层表面上的受影响层（第二步骤）。通过使用掩模（第三步骤）对接线层进行干式蚀刻。当从第二步骤到第三步骤进行移位时，不进行抽真空，并进行连续放电。

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