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1. 发明授权

US5832595A Method of modifying conductive lines of an electronic circuit board and its apparatus 失效
标题翻译：修改电子电路板导线及其装置的方法
公开(公告)号：US5832595A
公开(公告)日：1998-11-10
申请号：US260382
申请日：1994-06-14
申请人： Shigenobu Maruyama , Mikio Hongo , Haruhisa Sakamoto , Tateoki Miyauchi , Ryohei Satoh , Kiyoshi Matsui , Shinichi Kazui , Kaoru Katayama , Hiroshi Fukuda
发明人： Shigenobu Maruyama , Mikio Hongo , Haruhisa Sakamoto , Tateoki Miyauchi , Ryohei Satoh , Kiyoshi Matsui , Shinichi Kazui , Kaoru Katayama , Hiroshi Fukuda
IPC分类号： H01L23/538 , H01L21/48 , H01L23/12 , H05K1/09 , H05K3/00 , H05K3/02 , H05K3/10 , H05K3/22
CPC分类号： H01L21/485 , H05K3/225 , H05K1/095 , H05K2203/0769 , H05K2203/0783 , H05K2203/107 , H05K2203/108 , H05K2203/121 , H05K2203/173 , H05K2203/175 , H05K3/0017 , H05K3/027 , H05K3/102 , Y10T29/49124 , Y10T29/49718 , Y10T29/49732
摘要： A method of modifying an electronic circuit board by performing disconnection or connection of conductive lines at a specified or an arbitrary position of the conductive lines of the electronic circuit board thereby changing an electric circuit and of completely modifying an open pattern defect of the conductive lines or an insulator layer, and its device, wherein a first energy beam is irradiated to portions of repair terminals 9 and 9' which are intended to connect or disconnect, of conductive lines 5 and 5' in the electronic circuit board thereby removing a protection layer, making windows and exposing the terminals 9 and 9' for connection; a second energy beam is irradiated thereby disconnecting the repair terminals 9 and 9', or a metal piece for connecting is supplied to between the repair terminals 9 and 9' and applying an energy thereto thereby electrically connecting them; and the disconnected or connected windowed portion is locally coated with the insulator layer thereby modifying the conductive lines of the electronic circuit board. Further, windows 311 or 311' is formed in an insulating protection layer 310 on a conductive line connecting portion 308 formed in a couple or a conductive line disconnecting portion 309, a conductive line of the conductive line disconnecting portion is disconnected or a liquid material 312 for connecting conductive lines is supplied to the conductive line connecting portion 308, a metal layer 313 is precipitated by heating the liquid material 312 thereby connecting the conductive line connecting portion 308, and the window 311 or 311' is coated with an organic insulator layer.
摘要翻译：通过在电子电路板的导线的指定或任意位置执行导线的断开或连接来改变电子电路板的方法，从而改变电路并完全改变导电线的开路图案缺陷，或绝缘体层及其装置，其中第一能量束照射到旨在连接或断开电子电路板中的导线5和5'的修复端子9和9'的部分，从而去除保护层，制造窗户并露出端子9和9'用于连接; 照射第二能量束，从而断开维修端子9和9'，或者用于连接的金属片供应到修理端子9和9'之间并向其施加能量，从而电连接它们; 并且断开或连接的窗口部分局部地涂覆有绝缘体层，从而修改电子电路板的导线。此外，窗311或311'形成在形成在耦合或导线断路部分309中的导线连接部分308上的绝缘保护层310中，导线断开部分的导线被断开或液体材料312 用于连接导线的导线被提供给导线连接部分308，金属层313通过加热液体材料312而沉淀，从而连接导线连接部分308，并且窗311或311'被涂覆有机绝缘体层。

2. 发明授权

US5023407A Printed circuit board with a uniform conductive layer formed by equalization of metals therein 失效
标题翻译：具有通过均匀金属形成的均匀导电层的印刷电路板
公开(公告)号：US5023407A
公开(公告)日：1991-06-11
申请号：US390616
申请日：1989-08-07
申请人： Mitugu Shirai , Kaoru Katayama , Hideaki Sasaki , Shinichi Kazui , Ryohei Satoh , Tateoki Miyauchi , Mamoru Kobayashi
发明人： Mitugu Shirai , Kaoru Katayama , Hideaki Sasaki , Shinichi Kazui , Ryohei Satoh , Tateoki Miyauchi , Mamoru Kobayashi
IPC分类号： B23K1/20 , H01L21/48 , H01L21/52 , H01L21/60 , H01L23/50 , H05K1/03 , H05K1/09 , H05K3/24 , H05K3/34
CPC分类号： H05K3/246 , H01L21/4846 , H01L24/85 , H01L2224/45144 , H01L2224/48463 , H01L2224/85 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/15787 , H05K1/0306 , H05K1/092 , H05K2203/0723 , H05K2203/107 , H05K3/244 , H05K3/3457
摘要： A metal layer other than gold is formed on a ceramic substrate, a gold layer is further formed on said metal layer, and then a high density beam is applied to the treated substrate member. Thereby, the metal of the underlayer diffused through the grain boundaries of gold up to the surface of the gold layer by heat treatment or the like is uniformly mixed with gold to form an alloyed layer excellent in wettability to a solder. At the same time, nonmetallic impurities such as carbon adhering onto the surface of the gold layer are melted and removed.
摘要翻译：在陶瓷基板上形成金以外的金属层，在所述金属层上进一步形成金层，然后将高密度光束施加到处理过的基板部件。由此，通过热处理等将金的晶界扩散到金层的表面的底层的金属与金均匀混合，形成对焊料的润湿性优异的合金化层。同时，将金属杂质如粘附在金层表面上的碳熔化并除去。

3. 发明授权

US4687939A Method and apparatus for forming film by ion beam 失效
标题翻译：用离子束形成薄膜的方法和装置
公开(公告)号：US4687939A
公开(公告)日：1987-08-18
申请号：US668843
申请日：1984-11-06
申请人： Tateoki Miyauchi , Hiroshi Yamaguchi , Mikio Hongo , Katsuro Mizukoshi , Akira Shimase , Ryohei Satoh
发明人： Tateoki Miyauchi , Hiroshi Yamaguchi , Mikio Hongo , Katsuro Mizukoshi , Akira Shimase , Ryohei Satoh
IPC分类号： C23C14/48 , C23C14/22 , H01J37/305 , H01J37/317 , H01J37/00
CPC分类号： H01J37/3056 , C23C14/221 , H01J37/3178 , H01J2237/31749
摘要： An ion beam apparatus which comprises an enclosure defining a chamber of high vacuum. A crucible for producing vapor of a material, ionizing means, ion accelerating means, and a substrate to be deposited with the vaporized material to thereby form a film thereon are disposed within the chamber. An accelerating voltage is applied across the crucible and the accelerating means such that the crucible is of positive polarity while the accelerating means is of negative polarity. The material contained in the crucible is vaporized by heating. A pressure difference is maintained between the vapor pressure within the crucible and the vacuum chamber. The crucible is provided with a small hole for ejecting the vapor of the material into the vacuum chamber to thereby form atom clouds referred to as clusters under adiabatic expansion and supercooling, a part of the clusters being ionized through irradiation of electrons by the ionizing means and accelerated by the accelerating means so that the ionized and accelerated clusters deposit on the substrate to form a thin film thereon. The apparatus further comprises electrostatic optical system interposed between the cluster ionizing region and the substrate to be deposited with the ionized clusters, wherein the electrostatic optical system serves to focus the ionized clusters onto the element to form the thin film thereon through deposition of the ionized clusters.
摘要翻译：一种离子束装置，其包括限定高真空室的外壳。用于产生材料的蒸气的坩埚，离子化装置，离子加速装置以及待蒸发的材料沉积以形成其上的膜的基板设置在室内。在坩埚和加速装置之间施加加速电压，使得坩埚具有正极性，而加速装置是负极性的。包含在坩埚中的材料通过加热而蒸发。在坩埚内的蒸汽压力与真空室之间保持压力差。该坩埚设置有用于将材料的蒸气喷射到真空室中的小孔，从而在绝热膨胀和过冷却下形成称为簇的原子云，通过电离装置照射电子而使部分簇离子化; 通过加速装置加速，使得电离和加速的团簇沉积在基底上以在其上形成薄膜。该装置还包括插入群集电离区域和要沉积离子簇的基板之间的静电光学系统，其中静电光学系统用于将离子化的聚集体聚集到元件上以通过沉积离子簇而在其上形成薄膜。

4. 发明授权

US5151773A Electronic circuit apparatus comprising a structure for sealing an electronic circuit 失效
标题翻译：电子电路装置，包括用于密封电子电路的结构
公开(公告)号：US5151773A
公开(公告)日：1992-09-29
申请号：US676389
申请日：1991-03-28
申请人： Kiyoshi Matsui , Ryohei Satoh , Toshitada Netsu , Hideaki Sasaki , Mitugu Shirai , Kenichi Hamamura
发明人： Kiyoshi Matsui , Ryohei Satoh , Toshitada Netsu , Hideaki Sasaki , Mitugu Shirai , Kenichi Hamamura
IPC分类号： H01L23/10
CPC分类号： H01L23/10 , H01L2924/0002 , H01L2924/15312 , H01L2924/16152 , H01L2924/16195 , H01L2924/16315
摘要： An electronic circuit apparatus in which electronic circuit components are mounted to multiwiring substrate or the like for use with electronic circuits such as an LSI are sealed airtight by sealing units. The sealing unit is sealed by an upper board designated as an upper board sealing unit and a side board designated as a side board sealing unit, and the shape of the edge on cross section of the side board is convex or circular. Metallization is applied to solder joint portions between a substrate and a side board and between the side board and the upper board, and a predetermined solder joint height is provided by a support post to effect solder joining.
摘要翻译：将电子电路部件安装到多路接线基板等上以与诸如LSI的电子电路一起使用的电子电路装置通过密封单元密封。密封单元由指定为上板密封单元的上板和指定为侧板密封单元的侧板密封，侧板的横截面的边缘的形状为凸形或圆形。金属化应用于基板和侧板之间以及侧板和上板之间的焊接部分，并且由支撑柱提供预定的焊点高度以实现焊料接合。

5. 发明授权

US5923539A Multilayer circuit substrate with circuit repairing function, and electronic circuit device 失效
标题翻译：具有电路修复功能的多层电路基板和电子电路装置
公开(公告)号：US5923539A
公开(公告)日：1999-07-13
申请号：US547988
申请日：1995-10-25
申请人： Kiyoshi Matsui , Ryohei Satoh , Michifumi Kawai , Masashi Ohkubo , Yutaka Watanabe , Masakazu Yamamoto , Tsutomu Imai , Shinji Abe , Hiroyuki Hidaka
发明人： Kiyoshi Matsui , Ryohei Satoh , Michifumi Kawai , Masashi Ohkubo , Yutaka Watanabe , Masakazu Yamamoto , Tsutomu Imai , Shinji Abe , Hiroyuki Hidaka
IPC分类号： H01L23/538 , H05K1/00 , H05K3/22 , H05K1/11 , H05K1/14
CPC分类号： H01L23/5382 , H05K1/0292 , H01L2224/16225 , H01L2924/09701 , H01L2924/15311 , H01L2924/19107 , H05K1/0298 , H05K2201/10674 , H05K2201/10734
摘要： A multilayer circuit substrate with a circuit repairing function which has a circuit substrate having a circuit pattern and repair pattern on the inner layer via an inter-substrate insulation film and having circuit repairing areas for cutting and bonding the circuit on these patterns, a terminal bonding pad for bonding electronic circuit parts mounted on this substrate, and a conductive via hole for bonding said circuit pattern to the terminal bonding pad, wherein at least the circuit repairing area of the repair pattern and at least the circuit repairing area of said circuit pattern which are set on said inner layer are brought close to each other and positioned on the same plane.
摘要翻译：一种具有电路修复功能的多层电路基板，其具有经由基板间绝缘膜在内层具有电路图案和修复图案的电路基板，并且具有用于切割和接合这些图案上的电路的电路修复区域，端子接合用于接合安装在该基板上的电子电路部件的焊盘，以及用于将所述电路图案接合到端子焊盘的导电通孔，其中至少修复图案的电路修复区域和至少电路图案的电路修复区域设置在所述内层上彼此靠近并且位于同一平面上。

6. 发明授权

US5276289A Electronic circuit device and method of producing the same 失效
标题翻译：电子电路装置及其制造方法
公开(公告)号：US5276289A
公开(公告)日：1994-01-04
申请号：US674599
申请日：1991-03-25
申请人： Ryohei Satoh , Fumiyuki Kobayashi , Yutaka Watanabe , Tositada Netsu , Mitugu Shirai , Kenji Takeda , Masahide Harada , Kiyoshi Matsui , Hideaki Sasaki
发明人： Ryohei Satoh , Fumiyuki Kobayashi , Yutaka Watanabe , Tositada Netsu , Mitugu Shirai , Kenji Takeda , Masahide Harada , Kiyoshi Matsui , Hideaki Sasaki
IPC分类号： H01L23/02 , B23K35/30 , H01L21/60 , H01L23/10 , H01L23/16 , H01L23/538 , H01L25/065 , H05K3/34 , H05K1/00
CPC分类号： H01L24/81 , B23K35/30 , H01L23/10 , H01L23/16 , H01L23/5385 , H01L25/0655 , H05K3/3463 , H01L2224/16 , H01L2224/73253 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15311 , H01L2924/15312 , H01L2924/15787 , H01L2924/16152 , H01L2924/1616 , H01L2924/16195 , H01L2924/30107 , H05K2201/094 , H05K2201/10704 , H05K2201/10734
摘要： The present invention provides a multistep electronic circuit device comprising a plurality of parts and elements mechanically or electrically bonded in sequence to each other and to a substrate with a plurality of solders, which comprises as the parts and elements the substrate, input and output pins and LSI chips, and optionally packages and a cooler bonded through multistep bonding, the bondings of the parts and elements including at least one CCB bonding and at least one sealing, the solders each having a lower melting point than the heatproof temperature of the part or element to be bonded with the solder, and one of the solders having a melting point of at least 10.degree. C. lower than that of the other solder used at the bonding step immediately before. The solders used are selected from Au10-15wt%Ge alloy (melting point: 356.degree.-450.degree. C.), Pb1-5wt%Sn alloy (melting point: 314.degree.-325.degree. C.), Pb10-13wt%Sn alloy (melting point: 270.degree.-300.degree. C.), Au20wt%Sn alloy (melting point: 280.degree. C.), Sn3-6wt%Sb alloy (melting point: 232.degree.-243.degree. C.), Sn2-8wt%Ag alloy (melting point: 221.degree.-235.degree. C.), Sn35-55wt%Pb alloy (melting point: 183.degree. -200.degree. C.) and Sn45wt%Pb18wt%Bi (melting point: 135.degree.-160.degree. C.).
摘要翻译：本发明提供一种多步电子电路装置，其包括多个部件和元件，它们依次机械地或电连接地连接到具有多个焊料的基板上，该多个焊料包括作为部件和元件的基板，输入和输出销和 LSI芯片，以及任选的封装和通过多步接合结合的冷却器，包括至少一个CCB结合和至少一个密封的部件和元件的结合，每个具有比部件或元件的耐热温度低的熔点与焊料接合，并且其中一个焊料的熔点比紧接在之前的接合步骤中使用的其它焊料的熔点低至少10摄氏度。使用的焊料选自Au10-15wt％Ge合金（熔点：356〜450℃），Pb1-5wt％Sn合金（熔点：314〜325℃），Pb10-13wt％Sn合金（熔点：270〜300℃），Au20重量％Sn合金（熔点：280℃），Sn3-6重量％Sb合金（熔点：232度-243℃），Sn2-8重量％ Ag合金（熔点221〜235℃），Sn35-55wt％Pb合金（熔点：183〜200℃），Sn45wt％Pb18wt％Bi（熔点：135〜160℃））。

7. 发明申请

US20120053905A1 DESIGN WORKFLOW CONSTRUCTION APPARATUS, DESIGN WORKFLOW CONSTRUCTION METHOD, DESIGN SYSTEM, DESIGN METHOD, DESIGN WORKFLOW CONSTRUCTION PROGRAM, AND COMPUTER READABLE RECORDING MEDIUM IN WHICH DESIGN WORKFLOW CONSTRUCTION PROGRAM IS STORED 有权
标题翻译：设计工作流施工设备，设计工作流程施工方法，设计系统，设计方法，设计工作流程构造程序和设计工作流程构建程序存储的计算机可读记录介质
公开(公告)号：US20120053905A1
公开(公告)日：2012-03-01
申请号：US13201854
申请日：2010-02-16
申请人： Yoshiharu Iwata , Ryohei Satoh , Keiji Kudo , Atsushi Taya , Kazuya Okamoto , Hidenori Murata , Koichiro Atsumi , Eiji Arai , Eiji Morinaga
发明人： Yoshiharu Iwata , Ryohei Satoh , Keiji Kudo , Atsushi Taya , Kazuya Okamoto , Hidenori Murata , Koichiro Atsumi , Eiji Arai , Eiji Morinaga
IPC分类号： G06F17/50
CPC分类号： G06Q10/06 , G06Q10/0633
摘要： A design system (1) is provided with a function of acquiring a design specification of an object to be designed and an evaluation index for evaluating a value of the object to be designed in the design specification; a function of acquiring profile data of the object to be designed; a function (design order determining section (12)) of extracting entity design elements and important design variables from the profile data and prioritizing the entity design elements and the important design variables so as to construct a design workflow; a function (evaluation approach construction section (13)) of constructing an evaluation formula for performance/evaluation of a design result of each of the entity design elements in conformity with the design workflow; a function of finding an appropriate solution by performing automatic optimization while evaluating the design result with use of the evaluation index in accordance with the design workflow with which the evaluation formula is associated; and a function of outputting the appropriate solution thus found. This allows the object to be designed to be parametrically handled, and makes it possible to create a design workflow for efficiently finding an optimum design solution by properly combining a series of design elements and to find an appropriate solution with the use of the design workflow.
摘要翻译：设计系统（1）具有获取要设计的对象的设计规范和评估设计规范中要设计的对象的值的评估指标的功能; 获取要设计的对象的简档数据的功能; 从简档数据中提取实体设计元素和重要设计变量的功能（设计顺序确定部分（12）），并对实体设计元素和重要设计变量进行优先排序，从而构建设计工作流程; （评估方法构建部（13）），其根据设计工作流程构建用于对每个实体设计元素的设计结果进行性能/评估的评估公式; 通过根据与评估公式相关联的设计工作流程使用评估指数来评估设计结果，通过执行自动优化来找到适当的解决方案的功能; 以及输出由此找到的适当解决方案的功能。这允许将对象设计为参数化处理，并且可以创建设计工作流，以通过适当地组合一系列设计元素来有效地找到最佳设计解决方案，并使用设计工作流程找到适当的解决方案。

8. 发明授权

US07846641B2 Glass substrate having circuit pattern and process for producing the same 有权
标题翻译：具有电路图案的玻璃基板及其制造方法
公开(公告)号：US07846641B2
公开(公告)日：2010-12-07
申请号：US12143446
申请日：2008-06-20
申请人： Ryohei Satoh , Koji Nakagawa , Reo Usui , Kenji Tanaka , Satoru Takaki , Kenichi Ebata , Yumiko Aoki
发明人： Ryohei Satoh , Koji Nakagawa , Reo Usui , Kenji Tanaka , Satoru Takaki , Kenichi Ebata , Yumiko Aoki
IPC分类号： G03F7/26
CPC分类号： H05K3/28 , H01J9/02 , H01J11/12 , H01J11/34 , H05K1/0306 , H05K3/027 , H05K3/38 , H05K2201/0269 , Y10T428/24868
摘要： A process for producing a glass substrate having a circuit pattern is disclosed. The process includes forming a thin film layer on a glass substrate and then irradiating the thin film layer with laser light to form a circuit pattern on the glass substrate; depositing a low-melting point glass having a softening point of from 450 to 630° C. on the glass substrate having the circuit pattern formed thereon; and sintering the low-melting point glass to form a low-melting point glass layer which includes the low-melting point glass sintered on the glass substrate having the circuit pattern formed thereon and which forms a compatible layer between the glass substrate and the low-melting point glass layer.
摘要翻译：公开了一种具有电路图案的玻璃基板的制造方法。该方法包括在玻璃基板上形成薄膜层，然后用激光照射薄膜层，以在玻璃基板上形成电路图案; 在其上形成有电路图案的玻璃基板上沉积软化点为450〜630℃的低熔点玻璃; 并烧结低熔点玻璃以形成低熔点玻璃层，该低熔点玻璃层包括在其上形成有电路图案的玻璃基板上烧结的低熔点玻璃，并且在玻璃基板和低熔点玻璃之间形成相容层，熔点玻璃层。

9. 发明授权

US06919670B2 Rib structure for display device and its manufacture process 失效
标题翻译：显示器件的肋结构及其制造工艺
公开(公告)号：US06919670B2
公开(公告)日：2005-07-19
申请号：US09989063
申请日：2001-11-21
申请人： Yoshimi Kawanami , Yasuhiko Kunii , Tadashi Furukawa , Akihiro Fujinaga , Kazunori Ishizuka , Shoichi Iwanaga , Fumihiro Namiki , Ryohei Satoh
发明人： Yoshimi Kawanami , Yasuhiko Kunii , Tadashi Furukawa , Akihiro Fujinaga , Kazunori Ishizuka , Shoichi Iwanaga , Fumihiro Namiki , Ryohei Satoh
IPC分类号： H01J9/02 , H01J9/24 , H01J11/22 , H01J11/34 , H01J11/36 , H01J17/49
CPC分类号： H01J9/242 , H01J9/245 , H01J11/12 , H01J11/36 , H01J2211/366
摘要： A rib structure for a display device includes a light-transmissive rib structure containing therein a material absorbent of visible light so that a visible light absorption distance is 40 to 1200 μm (the visible light absorption distance L (μm) means a distance such that visible light decreases to exp(−T/L) times less in connection to the travel distance T (μm), that is, visible light is absorbed by 1-exp(−T/L)).
摘要翻译：用于显示装置的肋结构包括透光肋结构，其中包含可见光的材料吸收剂，使得可见光吸收距离为40至1200μm（可见光吸收距离L（mum）表示使得可见光相对于行驶距离T（mum），光减少到exp（-T / L）次，即可见光被1-exp（-T / L）吸收）。

10. 发明授权

US5865365A Method of fabricating an electronic circuit device 失效
标题翻译：制造电子电路装置的方法
公开(公告)号：US5865365A
公开(公告)日：1999-02-02
申请号：US761430
申请日：1996-12-06
申请人： Toru Nishikawa , Ryohei Satoh , Masahide Hara , Tetsuya Hayashida , Mitugu Shirai , Osamu Yamada , Hiroko Takehara , Yasuhiro Iwata , Mitsunori Tamura , Masahito Ijuin
发明人： Toru Nishikawa , Ryohei Satoh , Masahide Hara , Tetsuya Hayashida , Mitugu Shirai , Osamu Yamada , Hiroko Takehara , Yasuhiro Iwata , Mitsunori Tamura , Masahito Ijuin
IPC分类号： B23K1/00 , H01L21/48 , H01L21/56 , H01L21/60 , H01L21/68 , H01L23/498 , H05K3/34
CPC分类号： H01L24/12 , B23K1/0016 , H01L21/4853 , H01L21/563 , H01L21/6835 , H01L23/49816 , H01L24/11 , H01L24/29 , H01L24/81 , H01L24/83 , H05K3/3489 , B23K2201/40 , H01L2224/11003 , H01L2224/11334 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/29109 , H01L2224/29111 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2224/83805 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/3025 , H05K2203/0278 , H05K2203/041 , H05K2203/0435 , H05K2203/086 , H05K2203/087 , H05K2203/095 , H05K2203/1157 , H05K3/3426
摘要： A method of soldering used in fabricating an electronic circuit device employs an organic material supplied to at least one of the connecting members to be bonded. The connecting members are positioned in an oxidizing atmosphere, and heated in a nonoxidizing atmosphere to remove oxide and/or contamination layers present on the surface of presoldered portions or metallized bonding portions. By this method, fluxless soldering is performed, positional shifts are reduced, and high reliability of the soldering connections with reduction in residues after reflow are obtained.
摘要翻译：用于制造电子电路器件的焊接方法使用供应至待接合的至少一个连接部件的有机材料。连接构件位于氧化气氛中，并在非氧化气氛中加热以除去存在于预制部分或金属化粘合部分的表面上的氧化物和/或污染层。通过该方法，进行无焊剂焊接，位移偏移降低，并且获得了在回流之后具有减少残留物的焊接连接的高可靠性。

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