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1. 发明授权

US07397107B2 Ferromagnetic capacitor 有权
标题翻译：铁磁电容器
公开(公告)号：US07397107B2
公开(公告)日：2008-07-08
申请号：US11340278
申请日：2006-01-26
申请人： Kenneth D. Brennan , Satyavolu S. Papa Rao
发明人： Kenneth D. Brennan , Satyavolu S. Papa Rao
IPC分类号： H01L29/00
CPC分类号： H01L23/5227 , H01F17/0033 , H01F41/046 , H01L23/5223 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit capacitor having a bottom plate 50a, a dielectric layer 250′, and a ferromagnetic top plate 20a.
摘要翻译：具有底板50a，介电层250'和铁磁顶板20a的集成电路电容器。

2. 发明授权

US06911389B2 Self aligned vias in dual damascene interconnect, buried mask approach 有权
标题翻译：双镶嵌互连中的自对准通孔，掩埋掩模法
公开(公告)号：US06911389B2
公开(公告)日：2005-06-28
申请号：US10246061
申请日：2002-09-18
申请人： Kenneth D. Brennan , Paul Gillespie
发明人： Kenneth D. Brennan , Paul Gillespie
IPC分类号： H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/7681 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods are disclosed for forming vias, trenches, and interconnects through diffusion barrier, etch-stop, and dielectric materials for interconnection of electrical devices in dual damascene structures of a semiconductor device. A buried via mask at the etch-stop level provides openings with two or more adjacent via misalignment error regions merged into rectangular windows aligned orthogonal to a long axis of the underlying conductive features of a first metal level. The rectangular windows used together with openings in a hard mask form via portions, and the openings in the hard mask provide trench portions. Via and trench portions coincide during trench or via etch, as well as during hard mask or etch-stop layer etch together forming an interconnect cavity, which may then be filled with a conductive material to provide a conductive interconnect between the conductive feature of the first metal level and a second metal level.
摘要翻译：公开了用于通过扩散屏障，蚀刻停止和介电材料形成通孔，沟槽和互连的方法，用于半导体器件的双镶嵌结构中的电器件的互连。在蚀刻停止水平处的掩埋通孔掩模提供具有两个或更多个相邻的通孔未对准误差区域的开口，该相邻的通孔未对准误差区域被合并成与第一金属水平的底部导电特征的长轴正交排列的矩形窗口。与通过部分的硬掩模形式的开口一起使用的矩形窗口，并且硬掩模中的开口提供沟槽部分。通孔和沟槽部分在沟槽或通孔蚀刻期间重合，以及在硬掩模或蚀刻停止层蚀刻期间一起形成互连腔，然后可以用导电材料填充以在第一和第二导电特征之间提供导电互连金属水平和第二金属水平。

3. 发明授权

US06903918B1 Shielded planar capacitor 有权
标题翻译：屏蔽平面电容器
公开(公告)号：US06903918B1
公开(公告)日：2005-06-07
申请号：US10828139
申请日：2004-04-20
申请人： Kenneth D. Brennan
发明人： Kenneth D. Brennan
IPC分类号： H01G4/228
CPC分类号： H01G4/228 , H01L23/5223 , H01L23/5225 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A shielded planar capacitor structure (202) is discussed, formed within a Faraday cage (210) in an integrated circuit device (200). The capacitor structure (202) reduces parasitic capacitances within the integrated circuit device (200). The capacitor (202) comprises a capacitor stack (102) formed between a first and second metal layers (230,232) of the integrated circuit. The capacitor stack (102) has a first conductive layer formed from a third metal layer (106) disposed between the first and second metal layers (230,232) of the integrated circuit, a dielectric isolation layer (110) disposed upon the first conductive layer (106); and a second conductive layer (112) disposed upon the dielectric isolation layer (110) and overlying the first conductive layer (106). The structure (202) further has a first and second isolation layers (104,114) disposed upon opposite sides of the capacitor stack (102). The Faraday cage (210) is formed between the first and second metal layers (230,232) of the integrated circuit (200), comprising a first and second shield layers (402,414) each having a plurality of mutually electrically conductive spaced apart traces (404). The first and second isolation layers (404,414) and the capacitor stack (102,434) are sandwiched between the first and second shield layers (402,414). Conductive elements (432) are distributed around the periphery of the capacitor stack (102,434) and the first and second isolation layers (404,412). The conductive traces (424) of the first shield layer (402) are connected to the conductive traces (424) of the second shield layer (414) through the conductive elements (432).
摘要翻译：讨论了屏蔽平面电容器结构（202），其形成在集成电路器件（200）中的法拉第笼（210）内。电容器结构（202）降低集成电路器件（200）内的寄生电容。电容器（202）包括形成在集成电路的第一和第二金属层（230,232）之间的电容器堆叠（102）。电容器堆叠（102）具有由设置在集成电路的第一和第二金属层（230,232）之间的第三金属层（106）形成的第一导电层，设置在第一导电层上的介电隔离层（110） 106）; 以及设置在所述介电隔离层（110）上并且覆盖所述第一导电层（106）的第二导电层（112）。结构（202）还具有设置在电容器堆叠（102）的相对侧上的第一和第二隔离层（104,114）。法拉第笼（210）形成在集成电路（200）的第一和第二金属层（230,232）之间，包括第一和第二屏蔽层（402,414），每个屏蔽层具有多个相互导电的间隔开的迹线（404）。第一和第二隔离层（404,414）和电容器堆叠（102,434）夹在第一和第二屏蔽层（402,414）之间。导电元件（432）围绕电容器堆叠（102,434）和第一和第二隔离层（404,412）的周边分布。第一屏蔽层（402）的导电迹线（424）通过导电元件（432）连接到第二屏蔽层（414）的导电迹线（424）。

4. 发明授权

US06620727B2 Aluminum hardmask for dielectric etch 有权
标题翻译：用于电介质蚀刻的铝硬掩模
公开(公告)号：US06620727B2
公开(公告)日：2003-09-16
申请号：US09935450
申请日：2001-08-23
申请人： Kenneth D. Brennan
发明人： Kenneth D. Brennan
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76813
摘要： An aluminum hardmask (106, 214) is used for etching a dielectric layer (102, 210). A fluorine-based etch is used that does not etch the aluminum hardmask (106, 210). The aluminum hardmask (106, 214) is then removed by CMP.
摘要翻译：铝硬掩模（106,214）用于蚀刻介电层（102,210）。使用不蚀刻铝硬掩模（106,210）的氟基蚀刻。然后通过CMP去除铝硬掩模（106,214）。

5. 发明授权

US6074943A Sidewalls for guiding the via etch 失效
标题翻译：用于引导通孔蚀刻的侧壁
公开(公告)号：US6074943A
公开(公告)日：2000-06-13
申请号：US61320
申请日：1998-04-16
申请人： Kenneth D. Brennan , David B. Aldrich , Eden M. Zielinski , Peter S. McAnally
发明人： Kenneth D. Brennan , David B. Aldrich , Eden M. Zielinski , Peter S. McAnally
IPC分类号： H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76834 , H01L21/76852
摘要： A structure and method to direct the via 270 etch to the top of the interconnect 210, by using a sidewall layer 240, preferably TiN, and thus preventing the etching down the side of the interconnect 210 and exposure of materials residing between the interconnects 210.
摘要翻译：通过使用侧壁层240（优选为TiN）将通孔270蚀刻引导到互连210的顶部，从而防止互连210的侧面蚀刻和位于互连210之间的材料的暴露的结构和方法。

6. 发明授权

US07969274B2 Method to improve inductance with a high-permeability slotted plate core in an integrated circuit 有权
标题翻译：在集成电路中用高磁导率开槽板芯改善电感的方法
公开(公告)号：US07969274B2
公开(公告)日：2011-06-28
申请号：US12202665
申请日：2008-09-02
申请人： Kenneth D. Brennan , Satyavolu S. Papa Rao , Byron Williams
发明人： Kenneth D. Brennan , Satyavolu S. Papa Rao , Byron Williams
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01F2017/008 , H01L2924/0002 , H01L2924/3011 , Y10T29/49073 , H01L2924/00
摘要： An inductor structure (102) formed in an integrated circuit (100) is disclosed, and includes a first isolation layer (106) and a first core plate (104) disposed over or within the first isolation layer (106, 114). The first core plate (104) includes a plurality of electrically coupled conductive traces composed of a conductive ferromagnetic material layer. A second isolation layer (108) overlies the first isolation layer and an inductor coil (102) composed of a conductive material layer (118) is formed within the second isolation layer (108). Another core plate may be formed over the coil. The one or more core plates increase an inductance (L) of the inductor coil (102).
摘要翻译：公开了一种形成在集成电路（100）中的电感器结构（102），并且包括设置在第一隔离层（106,114）上或第一隔离层（106,114）内的第一隔离层（106）和第一芯板（104）。第一芯板（104）包括由导电铁磁材料层构成的多个电耦合导电迹线。第二隔离层（108）覆盖第一隔离层，并且在第二隔离层（108）内形成由导电材料层（118）构成的电感线圈（102）。可以在线圈上形成另一个芯板。一个或多个芯板增加电感线圈（102）的电感（L）。

7. 发明授权

US5998297A Method of etching copper or copper-doped aluminum 失效
标题翻译：蚀刻铜或铜掺杂铝的方法
公开(公告)号：US5998297A
公开(公告)日：1999-12-07
申请号：US947489
申请日：1997-10-10
申请人： Kenneth D. Brennan
发明人： Kenneth D. Brennan
IPC分类号： C23F4/00 , H01L21/02 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/44
CPC分类号： H01L21/02071 , C23F4/00 , H01L21/32136
摘要： An embodiment of the instant invention is a method of etching a conductive structure comprised of copper and overlying a semiconductor substrate, the method comprising the step of: subjecting the conductive structure to a combination of plasma, an etchant, and a gaseous aluminum source. Preferably, the conductive structure is comprised of aluminum and copper (more preferably, it is comprised of aluminum and 1 to 4% by weight copper) or it may be substantially comprised of substantially pure copper. In addition, the etchant is preferably introduced into the process chamber in a gaseous state and is comprised of Cl.sub.2. The gaseous aluminum source may be comprised of: DMAH, trimethylaluminum, dimethylalane, trimethylaminealine, dimethylethylaminealane, dimethylethylaminedimethylalane, or AlCl.sub.3.
摘要翻译：本发明的一个实施方案是蚀刻由铜构成并覆盖半导体衬底的导电结构的方法，该方法包括以下步骤：对导电结构进行等离子体，蚀刻剂和气态铝源的组合。优选地，导电结构由铝和铜组成（更优选地，其由铝和1至4重量％的铜组成），或者其可以基本上由基本上纯的铜组成。此外，蚀刻剂优选以气态引入处理室，并且由Cl 2组成。气态铝源可以由以下物质组成：DMAH，三甲基铝，二甲基亚砜，三甲基胺，二甲基乙基胺，二甲基乙基己基二甲基铝或AlCl 3。

8. 发明授权

US07118925B2 Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step 有权
标题翻译：在单个光罩步骤中制造铁磁感应芯和电容电极
公开(公告)号：US07118925B2
公开(公告)日：2006-10-10
申请号：US11008900
申请日：2004-12-10
申请人： Kenneth D. Brennan , Satyavolu S. Papa Rao
发明人： Kenneth D. Brennan , Satyavolu S. Papa Rao
IPC分类号： H01L21/00
CPC分类号： H01L23/5227 , H01F17/0033 , H01F41/046 , H01L23/5223 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil 50a, forming an etch stop layer 250′, forming a ferromagnetic capacitor top plate 20a and a ferromagnetic core 20b, forming a top portion of the induction coil 50b plus vias 50c that couple the top portion of the induction coil 50b to the bottom portion of the induction coil 50c.
摘要翻译：一种在半导体晶片上制造集成电路的方法。该方法包括形成电容器50a的底板和感应线圈50a的底部，形成蚀刻停止层250'，形成铁磁电容器顶板20A和铁磁芯20b，形成顶部感应线圈50b加上将感应线圈50b的顶部连接到感应线圈50c的底部的通孔50c。

9. 发明授权

US06465339B2 Technique for intralevel capacitive isolation of interconnect paths 有权
标题翻译：互连路径的层间电容隔离技术
公开(公告)号：US06465339B2
公开(公告)日：2002-10-15
申请号：US09216240
申请日：1998-12-18
申请人： Keith Brankner , Kenneth D. Brennan , Yvette Shaw
发明人： Keith Brankner , Kenneth D. Brennan , Yvette Shaw
IPC分类号： H01L2144
CPC分类号： H01L23/5222 , H01L21/31604 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A technique is described for providing cavities between the conducting paths of an integrated semiconductor circuit. These cavities can have air or a gas trapped therein to decrease the dielectric constant between two conducting paths. After forming the conducting paths, an etchable fill material formed between and over the conducting paths. An oxide cap is formed over the fill material. Conducting plugs, extending through the fill material and the oxide cap, and electrically coupled to the conducting paths are formed. A photo-resist layer applied over the conducting plugs and the oxide cap. The photo-resist layer is structured to permit access to the oxide cap between the conducting plugs. A “pin-hole” is fabricated through the oxide cap and the fill material exposed by the “pin-hole” is etched away. The “pin-hole” is plugged with additional oxide cap material and a surface is then formed on the oxide cap exposing the conducting plugs. This structure is then ready for additional processing.
摘要翻译：描述了一种用于在集成半导体电路的导电路径之间提供空腔的技术。这些空腔可以具有空气或被捕获在其中的气体以降低两个传导路径之间的介电常数。在形成导电路径之后，形成在导电路径之间和之上的可蚀刻填充材料。在填充材料上形成氧化物盖。形成延伸穿过填充材料和氧化物盖并且电耦合到导电路径的导电插头。施加在导电插塞和氧化物盖上的光致抗蚀剂层。光致抗蚀剂层被构造成允许接触导电插塞之间的氧化物盖。通过氧化物盖制造“针孔”，并且通过“针孔”暴露的填充材料被蚀刻掉。 “针孔”用附加的氧化物盖材料堵塞，然后在暴露导电插塞的氧化物盖上形成表面。然后，该结构可以进行额外的处理。

10. 发明授权

US07250334B2 Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode 有权
标题翻译：金属绝缘体金属（MIM）电容器制造与侧壁间隔和铝帽（ALCAP）顶部电极
公开(公告)号：US07250334B2
公开(公告)日：2007-07-31
申请号：US10909648
申请日：2004-07-31
申请人： Darius L. Crenshaw , Byron L. Williams , Alwin Tsao , Hisashi Shichijo , Satyavolu S. Papa Rao , Kenneth D. Brennan , Steven A. Lytle
发明人： Darius L. Crenshaw , Byron L. Williams , Alwin Tsao , Hisashi Shichijo , Satyavolu S. Papa Rao , Kenneth D. Brennan , Steven A. Lytle
IPC分类号： H01L21/8242
CPC分类号： H01L23/5223 , H01L21/76834 , H01L28/57 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.
摘要翻译：公开了形成MIM（金属绝缘金属）电容器的方法（10），其中即使电容器按比例缩小，也减轻了与铜扩散相关的不利影响。侧壁间隔物（156）抵靠着底部电极/铜扩散阻挡材料层（136）的边缘（137），电容器介电材料层（150）的边缘（151）和至少一些边缘（153）的顶层电极材料层。侧壁间隔物（156）是电介质或非导电的，并且减轻由于铜扩散而在板之间产生的“短路”电流。底部电极扩散阻挡材料（136）减轻了铜扩散和/或铜漂移，从而降低了设备过早失效的可能性。

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