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1. 发明申请

US20050255687A1 Plasma treatment for silicon-based dielectrics 有权
标题翻译：硅基电介质的等离子体处理
公开(公告)号：US20050255687A1
公开(公告)日：2005-11-17
申请号：US10843957
申请日：2004-05-11
申请人： Ping Jiang , Hyesook Hong , Ting Tsui , Robert Kraft
发明人： Ping Jiang , Hyesook Hong , Ting Tsui , Robert Kraft
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02123 , H01L21/0234 , H01L21/3105 , H01L21/316 , H01L21/76807 , H01L21/76808
摘要： An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over the spin-on-glass material (step 214), patterning the photoresist layer (step 214), and then etching the semiconductor wafer (step 216). Another embodiment of the invention is a method of manufacturing a dual damascene back-end layer on a semiconductor wafer. The method includes depositing spin-on-glass material over the dielectric layer and within the via holes (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over said spin-on-glass material (step 214), patterning the photoresist layer (step 214), and etching trench spaces (step 216).
摘要翻译：本发明的一个实施例是制造半导体晶片的方法。该方法包括在半导体晶片上沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤210），施加蒸发（步骤212），在旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214），然后蚀刻半导体晶片（步骤216）。本发明的另一实施例是在半导体晶片上制造双镶嵌后端层的方法。该方法包括在电介质层上和通孔内沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤（步骤212），在所述旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214）和蚀刻沟槽空间（步骤216）。

2. 发明授权

US07282436B2 Plasma treatment for silicon-based dielectrics 有权
标题翻译：硅基电介质的等离子体处理
公开(公告)号：US07282436B2
公开(公告)日：2007-10-16
申请号：US10843957
申请日：2004-05-11
申请人： Ping Jiang , Hyesook Hong , Ting Yiu Tsui , Robert Kraft
发明人： Ping Jiang , Hyesook Hong , Ting Yiu Tsui , Robert Kraft
IPC分类号： H01L21/4763
CPC分类号： H01L21/02123 , H01L21/0234 , H01L21/3105 , H01L21/316 , H01L21/76807 , H01L21/76808
摘要： An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over the spin-on-glass material (step 214), patterning the photoresist layer (step 214), and then etching the semiconductor wafer (step 216). Another embodiment of the invention is a method of manufacturing a dual damascene back-end layer on a semiconductor wafer. The method includes depositing spin-on-glass material over the dielectric layer and within the via holes (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over said spin-on-glass material (step 214), patterning the photoresist layer (step 214), and etching trench spaces (step 216).
摘要翻译：本发明的一个实施例是制造半导体晶片的方法。该方法包括在半导体晶片上沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤210），施加蒸发（步骤212），在旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214），然后蚀刻半导体晶片（步骤216）。本发明的另一实施例是在半导体晶片上制造双镶嵌后端层的方法。该方法包括在电介质层上和通孔内沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤（步骤212），在所述旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214）和蚀刻沟槽空间（步骤216）。

3. 发明授权

US06620560B2 Plasma treatment of low-k dielectric films to improve patterning 有权
公开(公告)号：US06620560B2
公开(公告)日：2003-09-16
申请号：US09975109
申请日：2001-10-11
申请人： Ping Jiang , Guoqiang Xing , Andrew J. McKerrow , Robert Kraft , Hyesook Hong
发明人： Ping Jiang , Guoqiang Xing , Andrew J. McKerrow , Robert Kraft , Hyesook Hong
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/31116 , H01L21/31138 , H01L21/76808 , H01L21/76826
摘要： Plasma treating a low-k dielectric layer (104) using an oxidation reaction (e.g., O2) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The plasma treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130, 132), during a rework of the pattern (130, 132), or between via and trench patterning to reduce resist poisoning.

4. 发明申请

US20070042599A1 Methods to facilitate etch uniformity and selectivity 有权
标题翻译：促进蚀刻均匀性和选择性的方法
公开(公告)号：US20070042599A1
公开(公告)日：2007-02-22
申请号：US11207493
申请日：2005-08-19
申请人： Ting Tsui , Jeannette Jacques , Robert Kraft , Ping Jiang
发明人： Ting Tsui , Jeannette Jacques , Robert Kraft , Ping Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76825 , H01L21/76807
摘要： A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.
摘要翻译：用基于能量的工艺制造半导体器件，其改变镶嵌工艺内的电介质层的蚀刻速率。第一互连层形成在半导体本体上。第一介电层形成在第一互连层上。改变第一介电层的蚀刻速率。在第一电介质层上形成第二电介质层。然后改变第二电介质层的蚀刻速率。执行沟槽蚀刻以在第二介电层内形成沟槽。执行通孔蚀刻以在第一介电层内形成通孔腔。空腔填充有导电材料，然后平坦化以除去多余的填充材料。

5. 发明授权

US07939400B2 Systems and methods that selectively modify liner induced stress 有权
标题翻译：系统和方法选择性地修改衬垫引起的应力
公开(公告)号：US07939400B2
公开(公告)日：2011-05-10
申请号：US12235766
申请日：2008-09-23
申请人： Ting Tsui , Satyavolu S. Papa Rao , Haowen Bu , Robert Kraft
发明人： Ting Tsui , Satyavolu S. Papa Rao , Haowen Bu , Robert Kraft
IPC分类号： H01L21/8238
CPC分类号： H01L21/76829 , H01L21/76825 , H01L21/823807 , H01L21/823828
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).
摘要翻译：本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。提供具有一个或多个区域的半导体器件（102）。应变诱导衬垫形成在半导体器件（104）上。将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

6. 发明授权

US07087518B2 Method of passivating and/or removing contaminants on a low-k dielectric/copper surface 有权
公开(公告)号：US07087518B2
公开(公告)日：2006-08-08
申请号：US10438566
申请日：2003-05-15
申请人： David Gerald Farber , William Wesley Dostalik , Robert Kraft , Andrew J. McKerrow , Kenneth Joseph Newton , Ting Tsui
发明人： David Gerald Farber , William Wesley Dostalik , Robert Kraft , Andrew J. McKerrow , Kenneth Joseph Newton , Ting Tsui
IPC分类号： H01L21/322
CPC分类号： H01L21/76829 , H01L21/306 , H01L21/31116 , H01L21/31144 , H01L21/314 , H01L21/76801
摘要： One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

7. 发明申请

US20070105368A1 Method of fabricating a microelectronic device using electron beam treatment to induce stress 审中-公开
标题翻译：使用电子束处理制造微电子器件以诱导应力的方法
公开(公告)号：US20070105368A1
公开(公告)日：2007-05-10
申请号：US11268036
申请日：2005-11-07
申请人： Ting Tsui , Andrew McKerrow , Haowen Bu , Robert Kraft
发明人： Ting Tsui , Andrew McKerrow , Haowen Bu , Robert Kraft
IPC分类号： H01L21/469
CPC分类号： H01L21/823807 , H01L21/3105 , H01L21/3148 , H01L21/3185 , H01L21/823864
摘要： The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure 230, subjecting the liner 310 to an electron beam 405 and depositing a pre-metal dielectric layer 415 over the liner 310.
摘要翻译：本发明在一个实施例中提供了一种制造微电子器件200的方法。该实施例包括在衬底210和栅极结构230上形成衬垫310，使衬垫310经受电子束405并在衬垫310上沉积预金属介电层415。

8. 发明申请

US20070032094A1 Energy beam treatment to improve packaging reliability 有权
标题翻译：能量束处理提高包装可靠性
公开(公告)号：US20070032094A1
公开(公告)日：2007-02-08
申请号：US11196985
申请日：2005-08-04
申请人： Ting Tsui , Andrew McKerrow , Satyavolu Rao , Robert Kraft
发明人： Ting Tsui , Andrew McKerrow , Satyavolu Rao , Robert Kraft
IPC分类号： H01L21/469
CPC分类号： H01L21/76825
摘要： The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.
摘要翻译：本发明提供一种提高介电层的硬度和/或弹性模量的方法以及集成电路的制造方法。提供电介质层的硬度和/或弹性模量的方法以及其它步骤包括提供具有硬度和弹性模量的电介质层，以及使电介质层经受能量束，从而使硬度或弹性模量增加值。

9. 发明申请

US20060264042A1 Interconnect structure including a silicon oxycarbonitride layer 审中-公开
标题翻译：互连结构包括硅碳氮氧化物层
公开(公告)号：US20060264042A1
公开(公告)日：2006-11-23
申请号：US11134698
申请日：2005-05-20
申请人： Laura Matz , Ting Tsui , Robert Kraft
发明人： Laura Matz , Ting Tsui , Robert Kraft
IPC分类号： H01L21/44
CPC分类号： H01L23/53295 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an interconnect structure, a method of manufacture therefore, and an integrated circuit including the same. In one embodiment of the present invention, the interconnect structure includes a conductive feature (150) located in or over a dielectric layer (140), and a silicon oxycarbonitride layer (160) located over the conductive feature (150).
摘要翻译：本发明提供互连结构，因此制造方法，以及包括其的集成电路。在本发明的一个实施例中，互连结构包括位于介电层（140）中或上方的导电特征（150）和位于导电特征（150）之上的硅碳氮氧化物层（160）。

10. 发明申请

US20060172481A1 Systems and methods that selectively modify liner induced stress 有权
标题翻译：系统和方法选择性地修改衬垫引起的应力
公开(公告)号：US20060172481A1
公开(公告)日：2006-08-03
申请号：US11049275
申请日：2005-02-02
申请人： Ting Tsui , Satyavolu Papa Rao , Haowen Bu , Robert Kraft
发明人： Ting Tsui , Satyavolu Papa Rao , Haowen Bu , Robert Kraft
IPC分类号： H01L21/469 , H01L21/8238
CPC分类号： H01L21/76829 , H01L21/76825 , H01L21/823807 , H01L21/823828
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).
摘要翻译：本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。提供具有一个或多个区域的半导体器件（102）。应变诱导衬垫形成在半导体器件（104）上。将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

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