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1. 发明申请

US20060099724A1 Memory cell with buffered layer 有权
标题翻译：带缓冲层的存储单元
公开(公告)号：US20060099724A1
公开(公告)日：2006-05-11
申请号：US11314222
申请日：2005-12-21
申请人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
发明人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

2. 发明申请

US20050054119A1 Buffered-layer memory cell 失效
标题翻译：缓冲层存储单元
公开(公告)号：US20050054119A1
公开(公告)日：2005-03-10
申请号：US10755654
申请日：2004-01-12
申请人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
发明人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
IPC分类号： H01L27/10 , G11C13/00 , H01L27/24 , H01L45/00 , H01L21/00 , G11C11/00 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的某些方面，半导体缓冲层由厚度在10至200纳米（nm）范围内的YBa2Cu3O7-X（YBCO），氧化铟（In2O3）或氧化钌（RuO2）形成。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr1-XCaXMnO3（PCMO）记忆膜，其中x在0.1和0.6之间的区域中，厚度在10至200nm的范围内。

3. 发明授权

US07256429B2 Memory cell with buffered-layer 有权
标题翻译：带缓冲层的存储单元
公开(公告)号：US07256429B2
公开(公告)日：2007-08-14
申请号：US11314222
申请日：2005-12-21
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

4. 发明授权

US07029924B2 Buffered-layer memory cell 失效
标题翻译：缓冲层存储单元
公开(公告)号：US07029924B2
公开(公告)日：2006-04-18
申请号：US10755654
申请日：2004-01-12
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

5. 发明申请

US20050266686A1 Method of substrate surface treatment for RRAM thin film deposition 有权
标题翻译： RRAM薄膜沉积的基板表面处理方法
公开(公告)号：US20050266686A1
公开(公告)日：2005-12-01
申请号：US10855088
申请日：2004-05-27
申请人： Wei-Wei Zhuang , Tingkai Li , Wei Pan , David Evans , Sheng Hsu
发明人： Wei-Wei Zhuang , Tingkai Li , Wei Pan , David Evans , Sheng Hsu
IPC分类号： C23C18/12 , C30B23/02 , C30B29/24 , H01L21/44 , H01L45/00
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1241 , C23C18/1283 , C30B23/02 , C30B29/24 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1608
摘要： A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.
摘要翻译：制造用于半导体器件的CMR薄膜的方法包括制备基于金属乙酸酯的乙酸溶液形式的CMR前体; 准备晶圆; 将晶片放置在旋涂室中; 根据以下步骤旋涂和加热晶片：将CMR前体注入旋涂室并在旋涂室中的晶片表面上; 将晶片加速至约1500RPM至3000RPM之间的旋转速度约30秒; 在约180℃的温度下烘烤晶片约1分钟; 将温度升高至约230℃; 在升温下烘烤晶片约1分钟; 在约500℃退火晶片约5分钟; 重复所述旋涂和加热步骤至少三次; 在约500℃至600℃之间将晶片退火约1至6小时，在干燥，干净的空气中进行退火; 并完成半导体器件。

6. 发明申请

US20050207265A1 Memory cell with an asymmetric crystalline structure 有权
标题翻译：具有不对称晶体结构的记忆单元
公开(公告)号：US20050207265A1
公开(公告)日：2005-09-22
申请号：US11130983
申请日：2005-05-16
申请人： Sheng Hsu , Tingkai Li , David Evans , Wei-Wei Zhuang , Wei Pan
发明人： Sheng Hsu , Tingkai Li , David Evans , Wei-Wei Zhuang , Wei Pan
IPC分类号： H01L27/10 , G11C11/15 , G11C13/00 , H01L45/00 , G11C8/02
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1625
摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.
摘要翻译：提供了非对称结构的存储单元和制造方法。该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度的第一层。在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

7. 发明申请

US20050037520A1 Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer 有权
标题翻译：当与高度结晶的种子层集成时，获得PCMO薄膜上的可逆电阻开关的方法
公开(公告)号：US20050037520A1
公开(公告)日：2005-02-17
申请号：US10640770
申请日：2003-08-13
申请人： Wei-Wei Zhuang , Tingkai Li , David Evans , Sheng Hsu , Wei Pan
发明人： Wei-Wei Zhuang , Tingkai Li , David Evans , Sheng Hsu , Wei Pan
IPC分类号： H01L27/04 , H01L21/20 , H01L21/822 , H01L45/00 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.
摘要翻译：当与高度结晶的种子层集成时，用于获得PCMO薄膜上的可逆电阻开关的方法包括通过MOCVD沉积高度结晶形式的PCMO的种子层，薄膜的厚度为约50埃至300埃通过旋转涂覆沉积种子层上的第二PCMO薄膜层，其厚度为约500埃至3000埃以形成组合的PCMO层; 通过施加约-4V至-5V之间的脉冲宽度在约75ns至1个音箱之间的负电脉冲来增加半导体器件中组合的PCMO膜的电阻; 并且通过施加脉冲宽度大于2.0个音箱的约+ 2.5V至+ 4V之间的正电脉冲来降低半导体器件中组合的PCMO层的电阻。

8. 发明申请

US20050239262A1 PCMO thin film with memory resistance properties 有权
标题翻译：具有记忆电阻特性的PCMO薄膜
公开(公告)号：US20050239262A1
公开(公告)日：2005-10-27
申请号：US10831677
申请日：2004-04-23
申请人： Wei-Wei Zhuang , Tingkai Li , Sheng Hsu , Fengyan Zhang
发明人： Wei-Wei Zhuang , Tingkai Li , Sheng Hsu , Fengyan Zhang
IPC分类号： H01L27/105 , H01L21/00 , H01L21/20 , H01L27/10 , H01L45/00 , H01L49/02
CPC分类号： H01L45/04 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.
摘要翻译：提供了一种用于形成具有结晶结构相关的记忆电阻性质的Pr 0.3M 3 Ca 0.7 MnO 3（PCMO）薄膜的方法。该方法包括：形成具有第一晶体结构的PCMO薄膜; 并且使用响应于第一晶体结构的脉冲极性来改变PCMO膜的电阻状态。在一个方面，第一晶体结构是无定形或弱结晶。然后，响应于单极脉冲改变PCMO膜的电阻状态。另一方面，PCMO薄膜具有多晶结构。然后，PCMO膜的电阻状态响应于双极性脉冲而改变。

9. 发明授权

US06849891B1 RRAM memory cell electrodes 有权
标题翻译： RRAM存储单元电极
公开(公告)号：US06849891B1
公开(公告)日：2005-02-01
申请号：US10730584
申请日：2003-12-08
申请人： Sheng Teng Hsu , Wei Pan , Fengyan Zhang , Wei-Wei Zhuang , Tingkai Li
发明人： Sheng Teng Hsu , Wei Pan , Fengyan Zhang , Wei-Wei Zhuang , Tingkai Li
IPC分类号： H01L21/28 , G11C13/00 , G11C16/02 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/22 , H01L29/68 , H01L39/00 , H01L43/08 , H01L45/00 , H01L29/94
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1675
摘要： A RRAM memory cell is formed on a silicon substrate having a operative junction therein and a metal plug formed thereon, includes a first oxidation resistive layer; a first refractory metal layer; a CMR layer; a second refractory metal layer; and a second oxidation resistive layer. A method of fabricating a multi-layer electrode RRAM memory cell includes preparing a silicon substrate; forming a junction in the substrate taken from the group of junctions consisting of N+ junctions and P+ junctions; depositing a metal plug on the junction; depositing a first oxidation resistant layer on the metal plug; depositing a first refractory metal layer on the first oxidation resistant layer; depositing a CMR layer on the first refractory metal layer; depositing a second refractory metal layer on the CMR layer; depositing a second oxidation resistant layer on the second refractory metal layer; and completing the RRAM memory cell.
摘要翻译：在其上具有工作结的硅衬底上形成有一个RRAM存储单元和形成在其上的金属插塞，包括第一氧化电阻层; 第一难熔金属层; 一个CMR层; 第二难熔金属层; 和第二氧化电阻层。制造多层电极RRAM存储单元的方法包括制备硅衬底; 从由N +结和P +结组成的接头组中形成在衬底中的结; 在接头上沉积金属塞; 在金属插塞上沉积第一抗氧化层; 在第一耐氧化层上沉积第一难熔金属层; 在第一难熔金属层上沉积CMR层; 在CMR层上沉积第二难熔金属层; 在所述第二难熔金属层上沉积第二抗氧化层; 并完成RRAM存储单元。

10. 发明申请

US20070284575A1 Metal/semiconductor/metal current limiter 有权
标题翻译：金属/半导体/金属限流器
公开(公告)号：US20070284575A1
公开(公告)日：2007-12-13
申请号：US11893402
申请日：2007-08-15
申请人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
发明人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
IPC分类号： H01L29/12
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).
摘要翻译：提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

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