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1. 发明授权

US07029924B2 Buffered-layer memory cell 失效
标题翻译：缓冲层存储单元
公开(公告)号：US07029924B2
公开(公告)日：2006-04-18
申请号：US10755654
申请日：2004-01-12
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

2. 发明授权

US07256429B2 Memory cell with buffered-layer 有权
标题翻译：带缓冲层的存储单元
公开(公告)号：US07256429B2
公开(公告)日：2007-08-14
申请号：US11314222
申请日：2005-12-21
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

3. 发明申请

US20060099724A1 Memory cell with buffered layer 有权
标题翻译：带缓冲层的存储单元
公开(公告)号：US20060099724A1
公开(公告)日：2006-05-11
申请号：US11314222
申请日：2005-12-21
申请人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
发明人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

4. 发明申请

US20050054119A1 Buffered-layer memory cell 失效
标题翻译：缓冲层存储单元
公开(公告)号：US20050054119A1
公开(公告)日：2005-03-10
申请号：US10755654
申请日：2004-01-12
申请人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
发明人： Sheng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David Evans , Masayuki Tajiri
IPC分类号： H01L27/10 , G11C13/00 , H01L27/24 , H01L45/00 , H01L21/00 , G11C11/00 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的某些方面，半导体缓冲层由厚度在10至200纳米（nm）范围内的YBa2Cu3O7-X（YBCO），氧化铟（In2O3）或氧化钌（RuO2）形成。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr1-XCaXMnO3（PCMO）记忆膜，其中x在0.1和0.6之间的区域中，厚度在10至200nm的范围内。

5. 发明授权

US06824814B2 Preparation of LCPMO thin films which have reversible resistance change properties 有权
标题翻译：制备具有可逆电阻变化特性的LCPMO薄膜
公开(公告)号：US06824814B2
公开(公告)日：2004-11-30
申请号：US10153841
申请日：2002-05-21
申请人： Wei-Wei Zhuang , Sheng Teng Hsu , Wei Pan , Masayuki Tajiri
发明人： Wei-Wei Zhuang , Sheng Teng Hsu , Wei Pan , Masayuki Tajiri
IPC分类号： B05D512
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1283 , G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method of forming a perovskite thin film includes preparing a perovskite precursor solution; preparing a silicon substrate for deposition of a perovskite thin film, including forming a bottom electrode on the substrate; securing the substrate in a spin-coating apparatus and spinning the substrate at a predetermined spin rate; injecting a perovskite precursor solution into the spin-coating apparatus thereby coating the substrate with the perovskite precursor solution to form a coated substrate; baking the coated substrate at temperatures which increase incrementally from about 90° C. to 300° C.; and annealing the coated substrate at a temperature of between about 500° C. to 800° C. for between five minutes to fifteen minutes.
摘要翻译：形成钙钛矿薄膜的方法包括制备钙钛矿前体溶液; 制备用于沉积钙钛矿薄膜的硅衬底，包括在衬底上形成底电极; 将基材固定在旋涂装置中并以预定的旋转速率旋转基材; 将钙钛矿前体溶液注入到旋涂装置中，由此用钙钛矿前体溶液涂覆基材以形成涂布的基材; 在从约90℃增加到300℃的温度下烘烤涂覆的基材; 并在约500℃至800℃的温度下退火涂覆的基材5分钟至15分钟。

6. 发明申请

US20120219675A1 APPARATUS AND METHOD FOR MANUFACTURING PET FOOD 有权
标题翻译：制造PET食品的装置和方法
公开(公告)号：US20120219675A1
公开(公告)日：2012-08-30
申请号：US13368183
申请日：2012-02-07
申请人： Yoshiharu Okamoto , Masayuki Tajiri
发明人： Yoshiharu Okamoto , Masayuki Tajiri
IPC分类号： A23P1/12 , A23P1/08 , A23L3/40 , H05B6/64 , A23K1/00
CPC分类号： A23N17/004 , A23K40/20 , A23K40/25 , A23K50/40 , A23N17/005
摘要： A manufacturing apparatus and a manufacturing method of pet food are provided. The manufacturing apparatus comprises a material inlet through which a kneaded material is fed, the kneaded material being obtained through kneading a raw pet food material; an extrusion molding section configured to extrude the kneaded material through an extruding outlet; a cutter configured to cut the kneaded material extruded through the extruding outlet at desired intervals to form material grains; a reservoir disposed in a location to receive the material grains falling due to the cutting; an agitating section provided in the reservoir and configured to agitate the material grains; a heating section configured to heat the material grains while the material grains are agitated by the agitating section; and a drying section configured to dry the material grains within the reservoir after the heating.
摘要翻译：提供宠物食品的制造装置和制造方法。该制造装置包括通过捏合原料的宠物食材得到的捏合材料的材料入口，挤出成形部，其构造成通过挤压出口挤出混炼物; 切割器，其被构造成以期望的间隔切割通过挤出出口挤出的捏合材料以形成材料颗粒; 设置在容纳由于切割而落下的材料颗粒的位置的储存器; 搅拌部，设置在所述储存器中并且构造成搅拌所述材料颗粒; 加热部，其构造成在所述搅拌部搅拌所述材料粒子的同时加热所述材料粒子; 以及干燥部，其被配置为在加热之后干燥储存器内的材料颗粒。

7. 发明申请

US20140084346A1 SWITCHING ELEMENT 有权
标题翻译：开关元件
公开(公告)号：US20140084346A1
公开(公告)日：2014-03-27
申请号：US14119934
申请日：2012-04-02
申请人： Masayuki Tajiri
发明人： Masayuki Tajiri
IPC分类号： H01L29/778 , H01L29/20 , H01L29/205
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/205 , H01L29/41725 , H01L29/42316 , H01L29/66462 , H01L29/7787
摘要： Provided is a switching element capable of effectively preventing a collapse phenomenon. A switching element (la) includes an electron running layer (12), an electron supplying layer (13) formed on an upper surface of the electron running layer (12), having a band gap larger than that of the electron running layer (12), and forming a heterojunction with the electron running layer (12), a recombination layer (17) formed on an upper surface of the electron supplying layer (13) and having a band gap smaller than that of the electron supplying layer (13), a source electrode (14) and a drain electrode (15) at least partially formed on the upper surface of the electron running layer (12), and a gate electrode (16) at least partially formed on the upper surface of the electron supplying layer (13) and arranged between the source electrode (14) and the drain electrode (15). When the switching element (la) is in an off state, electrons and holes are recombined in the recombination layer (17).
摘要翻译：提供能够有效地防止塌陷现象的开关元件。开关元件（1a）包括电子运行层（12），形成在电子运行层（12）的上表面上的电子供给层（13），其带隙大于电子运行层（12）的带隙），与电子运行层（12）形成异质结，在电子供给层（13）的上表面上形成并且具有小于电子供给层（13）的带隙的复合层（17），至少部分地形成在电子运行层（12）的上表面上的源电极（14）和漏电极（15），以及至少部分地形成在电子供给层的上表面上的栅电极层（13）并且布置在源电极（14）和漏电极（15）之间。当开关元件（1a）处于截止状态时，电子和空穴在复合层（17）中再结合。

8. 发明授权

US07397688B2 Nonvolatile variable resistor, memory device, and scaling method of nonvolatile variable resistor 有权
标题翻译：非易失性可变电阻器，存储器件和易失性可变电阻器的定标方法
公开(公告)号：US07397688B2
公开(公告)日：2008-07-08
申请号：US10700467
申请日：2003-11-05
申请人： Masayuki Tajiri
发明人： Masayuki Tajiri
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/72 , G11C2213/79 , H01L27/101 , H01L27/2409 , H01L27/2436 , H01L28/20 , H01L45/04 , H01L45/1226 , H01L45/147
摘要： Provided are a nonvolatile variable resistor with a structure capable of suppressing an increase in resistance in a case where scaling is applied to reduce a projected area on a plane, a memory device using the nonvolatile variable resistor, and a scaling method of a nonvolatile variable resistor. A first electrode and a second electrode formed on a substrate face each other in a direction of a surface of the substrate. The first electrode is used as an inner electrode, a nonvolatile variable resistance body is formed on an outer surface of the first electrode and the second electrode is formed as an outer electrode on an outer surface of the nonvolatile variable resistance body.
摘要翻译：提供了一种非易失性可变电阻器，其具有能够抑制在施加缩放以减小平面上的投影面积的情况下的电阻增加的结构，使用非易失性可变电阻器的存储器件以及非易失性可变电阻器的缩放方法。形成在基板上的第一电极和第二电极在基板表面的方向上彼此面对。第一电极用作内部电极，在第一电极的外表面上形成非易失性可变电阻体，并且在非易失性可变电阻体的外表面上形成第二电极作为外部电极。

9. 发明授权

US06956280B2 Integrated circuit apparatus and neuro element 有权
标题翻译：集成电路设备和神经元件
公开(公告)号：US06956280B2
公开(公告)日：2005-10-18
申请号：US10397090
申请日：2003-03-25
申请人： Masayuki Tajiri , Nobuyoshi Awaya
发明人： Masayuki Tajiri , Nobuyoshi Awaya
IPC分类号： H01L27/10 , G06N3/063 , G11C11/54 , G11C13/00 , H01L49/00 , H01L29/00
CPC分类号： G11C13/0007 , G06N3/063 , G11C11/54 , G11C2213/31
摘要： Input signals are weighted by weighting means composed of variable resistors, each made of an oxide thin film with a perovskite structure containing manganese, which changes resistance at room temperature according to the cumulative number of times a pulse voltage was applied and holds the resistance in a nonvolatile manner. Then, the weighted signals are inputted to an arithmetic unit. The oxide thin film used as each of the variable resistors changes its resistance, according to the cumulative number of times the input pulse was applied, and further holds the resistance in a nonvolatile manner even after the power supply is cut off. Thus, by changing the weighting factor according to the cumulative number of times the pulse voltage was applied, a neuro element more resembling a neuron of the human being is realized.
摘要翻译：输入信号通过由可变电阻器组成的加权装置加权，每个可变电阻器由具有包含锰的钙钛矿结构的氧化物薄膜制成，其根据施加脉冲电压的累积次数在室温下改变电阻并且将电阻保持在非挥发性。然后，加权信号被输入到运算单元。用作各可变电阻器的氧化物薄膜根据施加输入脉冲的累积次数而改变其电阻，并且即使在电源被切断之后也进一步保持电阻以非易失性方式。因此，通过根据施加脉冲电压的累积次数来改变加权因子，实现了更类似于人的神经元的神经元素。

10. 发明授权

US09171945B2 Switching element utilizing recombination 有权
标题翻译：利用重组的开关元件
公开(公告)号：US09171945B2
公开(公告)日：2015-10-27
申请号：US14119934
申请日：2012-04-02
申请人： Masayuki Tajiri
发明人： Masayuki Tajiri
IPC分类号： H01L29/778 , H01L29/20 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/205
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/205 , H01L29/41725 , H01L29/42316 , H01L29/66462 , H01L29/7787
摘要： Provided is a switching element capable of effectively preventing a collapse phenomenon. A switching element (1a) includes an electron running layer (12), an electron supplying layer (13) formed on an upper surface of the electron running layer (12), having a band gap larger than that of the electron running layer (12), and forming a heterojunction with the electron running layer (12), a recombination layer (17) formed on an upper surface of the electron supplying layer (13) and having a band gap smaller than that of the electron supplying layer (13), a source electrode (14) and a drain electrode (15) at least partially formed on the upper surface of the electron running layer (12), and a gate electrode (16) at least partially formed on the upper surface of the electron supplying layer (13) and arranged between the source electrode (14) and the drain electrode (15). When the switching element (1a) is in an off state, electrons and holes are recombined in the recombination layer (17).
摘要翻译：提供能够有效地防止塌陷现象的开关元件。开关元件（1a）包括电子运行层（12），形成在电子运行层（12）的上表面上的电子供给层（13），其带隙大于电子运行层（12）的带隙），与电子运行层（12）形成异质结，在电子供给层（13）的上表面上形成并且具有小于电子供给层（13）的带隙的复合层（17），至少部分地形成在电子运行层（12）的上表面上的源电极（14）和漏电极（15），以及至少部分地形成在电子供给层的上表面上的栅电极层（13）并且布置在源电极（14）和漏电极（15）之间。当开关元件（1a）处于截止状态时，电子和空穴在复合层（17）中再结合。

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