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1. 发明授权

US07770049B1 Controller for clock skew determination and reduction based on a lead count over multiple clock cycles 有权
标题翻译：控制器用于在多个时钟周期内基于引脚数的时钟偏差确定和减少
公开(公告)号：US07770049B1
公开(公告)日：2010-08-03
申请号：US11385328
申请日：2006-03-21
申请人： Shawn Searles , Scott C. Johnson , Donald Walters , Ravinder Rachala
发明人： Shawn Searles , Scott C. Johnson , Donald Walters , Ravinder Rachala
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： Clock skew may be detected measured and compensated for using phase detectors and variable delay adjusters. Phase detectors may be distributed throughout a clock distribution network and may be configured to analyze two clock signals to determine how often one signal leads the other. The output of the phase detectors may be measured and counted over a large number of clock cycles. The difference between the number of times one signal leads or lags behind the other may be used to determine the amount of delay to apply to the leading clock signal in order to minimize (reduce) skew between the two clock signals. The same techniques for detecting and measuring clock skew may also be used to detect and measure jitter in the clock signals. By configuring variable delay adjusters on clock signals, the amount of jitter in the clock signals can be measured or characterized.
摘要翻译：可以使用相位检测器和可变延迟调节器测量和补偿时钟偏移。相位检测器可以分布在整个时钟分配网络中，并且可以被配置为分析两个时钟信号以确定一个信号引导另一个信号的频率。可以在大量时钟周期上测量和计数相位检测器的输出。可以使用一个信号引导或滞后于另一个信号的次数之间的差异来确定应用于前导时钟信号的延迟量，以便最小化（减少）两个时钟信号之间的偏差。用于检测和测量时钟偏移的相同技术也可用于检测和测量时钟信号中的抖动。通过在时钟信号上配置可变延迟调节器，可以测量或表征时钟信号中的抖动量。

2. 发明授权

US07765425B1 Incrementally adjustable skew and duty cycle correction for clock signals within a clock distribution network 有权
标题翻译：对时钟分配网络内的时钟信号进行增量可调偏移和占空比校正
公开(公告)号：US07765425B1
公开(公告)日：2010-07-27
申请号：US11385329
申请日：2006-03-21
申请人： Shawn Searles , Donald Walters , Ravinder Rachala , Scott C. Johnson
发明人： Shawn Searles , Donald Walters , Ravinder Rachala , Scott C. Johnson
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A system and method for using variable delay adjusters located at various points across an integrated circuit to measure clock skew and jitter for clock signals of the integrated circuit. A delay controller of the integrated circuit may measure and compensate for clock skew detected between two clock signals by configuring variable delay adjusters located inline with the respective clock signals. Such a delay controller may also use the variable delay adjusters to correct duty cycle errors in a clock signal and may further utilize the variable delay adjusters to measure and characterize jitter detected on the clock signals.
摘要翻译：一种用于使用位于集成电路上的各个点的可变延迟调节器来测量集成电路的时钟信号的时钟偏移和抖动的系统和方法。集成电路的延迟控制器可以通过配置与各个时钟信号在一起的可变延迟调节器来测量和补偿在两个时钟信号之间检测到的时钟偏差。这样的延迟控制器还可以使用可变延迟调整器来校正时钟信号中的占空比误差，并且还可以利用可变延迟调节器来测量和表征在时钟信号上检测到的抖动。

3. 发明授权

US07652524B2 Voltage source for gate oxide protection 有权
标题翻译：电压源用于栅极氧化物保护
公开(公告)号：US07652524B2
公开(公告)日：2010-01-26
申请号：US12018297
申请日：2008-01-23
申请人： Dimitry Patent , Ravinder Rachala , Shawn Searles , Lena Ahlen , Matthew Cooke
发明人： Dimitry Patent , Ravinder Rachala , Shawn Searles , Lena Ahlen , Matthew Cooke
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/262
摘要： An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit. The source terminals of each of the first and second transistors are coupled together to form a third supply voltage node.
摘要翻译：电子电路。电子电路包括耦合到第一电源电压节点和第二电源电压节点的第一电路支路。第一电路支路包括被配置为产生第一参考电流的第一参考电流电路和被配置为产生第二参考电流的第二参考电流电路。电子电路还包括与第一电路支路并联耦合的第二电路支路。第二电路支路包括耦合以与第一参考电流电路形成电流镜的第一晶体管，以及耦合以与第二参考电流电路形成电流镜的第二晶体管。第一和第二晶体管中的每一个的源极端子耦合在一起以形成第三电源电压节点。

4. 发明申请

US20090184696A1 VOLTAGE SOURCE FOR GATE OXIDE PROTECTION 有权
标题翻译：栅氧化物保护电压源
公开(公告)号：US20090184696A1
公开(公告)日：2009-07-23
申请号：US12018297
申请日：2008-01-23
申请人： Dimitry Patent , Ravinder Rachala , Shawn Searles , Lena Ahlen , Matthew Cooke
发明人： Dimitry Patent , Ravinder Rachala , Shawn Searles , Lena Ahlen , Matthew Cooke
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit. The source terminals of each of the first and second transistors are coupled together to form a third supply voltage node
摘要翻译：电子电路。电子电路包括耦合到第一电源电压节点和第二电源电压节点的第一电路支路。第一电路支路包括被配置为产生第一参考电流的第一参考电流电路和被配置为产生第二参考电流的第二参考电流电路。电子电路还包括与第一电路支路并联耦合的第二电路支路。第二电路支路包括耦合以与第一参考电流电路形成电流镜的第一晶体管，以及耦合以与第二参考电流电路形成电流镜的第二晶体管。第一和第二晶体管中的每一个的源极端子耦合在一起以形成第三电源电压节点

5. 发明授权

US08719598B2 Power OK distribution for multi-voltage chips 有权
标题翻译：多功能电源芯片的Power OK配置
公开(公告)号：US08719598B2
公开(公告)日：2014-05-06
申请号：US12828880
申请日：2010-07-01
申请人： Shawn Searles , Scott C. Johnson , Grace I. Chuang
发明人： Shawn Searles , Scott C. Johnson , Grace I. Chuang
IPC分类号： G06F1/28 , G06F1/30
CPC分类号： G06F1/28
摘要： A method and apparatus for powering up an integrated circuit (IC). An IC includes a plurality of power domains each coupled to receive power from one of a plurality of power sources. Each power domain includes a power-sensing unit. A power-sensing unit in a first one of the plurality of power domains is coupled to receive a first power ok signal from an upstream power domain, and is configured to assert a second power ok signal to be provided to a second power domain. A power-sensing unit in the second power domain is coupled to detect the presence of voltage in the first power domain, and to receive the first power ok signal. When the power-sensing unit in the second power domain has both sensed the presence of power in the first power domain and received the second power ok signal, a third power ok signal is asserted.
摘要翻译：一种用于为集成电路（IC）供电的方法和装置。 IC包括多个功率域，每个功率域被耦合以从多个电源之一接收功率。每个功率域包括功率感测单元。多个功率域中的第一个功率区中的功率感测单元被耦合以从上游功率域接收第一功率ok信号，并且被配置为断言要提供给第二功率域的第二功率ok信号。耦合第二功率域中的功率感测单元以检测第一功率域中的电压的存在并接收第一功率ok信号。当第二功率域中的功率感测单元已经感测到在第一功率域中存在功率并且接收到第二功率ok信号时，断言第三功率确认信号。

6. 发明申请

US20100275051A1 POWER OK DISTRIBUTION FOR MULTI-VOLTAGE CHIPS 有权
标题翻译：多功能电源的POWER OK分配
公开(公告)号：US20100275051A1
公开(公告)日：2010-10-28
申请号：US12828880
申请日：2010-07-01
申请人： Shawn Searles , Scott C. Johnson , Grace I. Chuang
发明人： Shawn Searles , Scott C. Johnson , Grace I. Chuang
IPC分类号： G06F1/26
CPC分类号： G06F1/28
摘要： A method and apparatus for powering up an integrated circuit (IC). An IC includes a plurality of power domains each coupled to receive power from one of a plurality of power sources. Each power domain includes a power-sensing unit. A power-sensing unit in a first one of the plurality of power domains is coupled to receive a first power ok signal from an upstream power domain, and is configured to assert a second power ok signal to be provided to a second power domain. A power-sensing unit in the second power domain is coupled to detect the presence of voltage in the first power domain, and to receive the first power ok signal. When the power-sensing unit in the second power domain has both sensed the presence of power in the first power domain and received the second power ok signal, a third power ok signal is asserted.
摘要翻译：一种用于为集成电路（IC）供电的方法和装置。 IC包括多个功率域，每个功率域被耦合以从多个电源之一接收功率。每个功率域包括功率感测单元。多个功率域中的第一个功率域中的功率感测单元被耦合以从上游功率域接收第一功率ok信号，并且被配置为断言要提供给第二功率域的第二功率ok信号。耦合第二功率域中的功率感测单元以检测第一功率域中的电压的存在并接收第一功率ok信号。当第二功率域中的功率感测单元已经感测到在第一功率域中存在功率并且接收到第二功率ok信号时，断言第三功率确认信号。

7. 发明授权

US07770037B2 Power ok distribution for multi-voltage chips 有权
标题翻译： Power电压分配多电压芯片
公开(公告)号：US07770037B2
公开(公告)日：2010-08-03
申请号：US11408226
申请日：2006-04-20
申请人： Shawn Searles , Scott C. Johnson , Grace I. Chuang
发明人： Shawn Searles , Scott C. Johnson , Grace I. Chuang
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/28
摘要： A method and apparatus for powering up an integrated circuit (IC). An IC includes a plurality of power domains each coupled to receive power from one of a plurality of power sources. Each power domain includes a power-sensing unit. A power-sensing unit in a first one of the plurality of power domains is coupled to receive a first power ok signal from an upstream power domain, and is configured to assert a second power ok signal to be provided to a second power domain. A power-sensing unit in the second power domain is coupled to detect the presence of voltage in the first power domain, and to receive the first power ok signal. When the power-sensing unit in the second power domain has both sensed the presence of power in the first power domain and received the second power ok signal, a third power ok signal is asserted.
摘要翻译：一种用于为集成电路（IC）供电的方法和装置。 IC包括多个功率域，每个功率域被耦合以从多个电源之一接收功率。每个功率域包括功率感测单元。多个功率域中的第一个功率区中的功率感测单元被耦合以从上游功率域接收第一功率ok信号，并且被配置为断言要提供给第二功率域的第二功率ok信号。耦合第二功率域中的功率感测单元以检测第一功率域中的电压的存在并接收第一功率ok信号。当第二功率域中的功率感测单元已经感测到在第一功率域中存在功率并且接收到第二功率ok信号时，断言第三功率确认信号。

8. 发明授权

US08729944B2 Clock generator with integrated phase offset programmability 有权
标题翻译：具有集成相位偏移可编程性的时钟发生器
公开(公告)号：US08729944B2
公开(公告)日：2014-05-20
申请号：US13333011
申请日：2011-12-21
申请人： Bruce A. Doyle , Emerson S. Fang , Alvin L. Loke , Shawn Searles , Stephen F. Greenwood
发明人： Bruce A. Doyle , Emerson S. Fang , Alvin L. Loke , Shawn Searles , Stephen F. Greenwood
IPC分类号： H03K5/13
CPC分类号： H03K3/0322 , H03L7/0996
摘要： A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.
摘要翻译：装置可以包括第一，第二和第三缓冲级。该装置还可以包括选择器电路，用于选择性地输出第二缓冲级的输出或第三缓冲级的输出之一。器件可以包括输出以提供第一时钟信号，其中第一时钟信号是第一缓冲器级的输出，并且器件还包括输出以提供第二时钟信号，其中第二时钟信号是选择器电路。

9. 发明授权

US08356155B2 Dynamic RAM Phy interface with configurable power states 有权
标题翻译：动态RAM Phy接口具有可配置的电源状态
公开(公告)号：US08356155B2
公开(公告)日：2013-01-15
申请号：US12910412
申请日：2010-10-22
申请人： Shawn Searles , Nicholas T. Humphries , Brian W. Amick , Richard W. Reeves , Hanwoo Cho , Ronald L. Pettyjohn
发明人： Shawn Searles , Nicholas T. Humphries , Brian W. Amick , Richard W. Reeves , Hanwoo Cho , Ronald L. Pettyjohn
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F1/3275 , G06F13/1689 , G06F13/4072 , G06F13/4086 , Y02D10/14
摘要： A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.
摘要翻译：公开了物理存储器接口（Phy）和操作方法。 Phy接口包括被配置为接收第一功率上下文和第二功率上下文的命令和状态寄存器（CSR）。选择电路被配置为在第一和第二电源上下文之间切换。提供了多个可调延迟元件，每个延迟元件具有响应于所选功率上下文的延迟时间。配置的第一组CSR可以存储第一功率上下文，并且配置的第二组CSR可以存储第二功率上下文。 Phy接口还可以包括多个驱动器，每个驱动器响应于所选择的功率上下文具有可选择的驱动强度。 Phy接口还可以包括多个接收器，每个接收器具有响应于所选择的功率上下文的可选择的终端阻抗。在功率上下文之间切换可导致延迟元件的调整，一个或多个驱动器/接收器的驱动强度和/或终端阻抗。

10. 发明申请

US20090244997A1 Method for Training Dynamic Random Access Memory (DRAM) Controller Timing Delays 有权
标题翻译：动态随机存取存储器（DRAM）控制器定时延迟的方法
公开(公告)号：US20090244997A1
公开(公告)日：2009-10-01
申请号：US12059653
申请日：2008-03-31
申请人： Shawn Searles , Tahsin Askar , Thomas H. Hamilton , Oswin Housty
发明人： Shawn Searles , Tahsin Askar , Thomas H. Hamilton , Oswin Housty
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/20 , G11C7/222 , G11C11/4072 , G11C11/4076 , G11C11/4093 , G11C2207/2254
摘要： Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).
摘要翻译：训练了双数据速率（DDR）动态随机存取存储器（DRAM）控制器（114,116）中的定时延迟。确定通过接收使能延迟值的左边缘（530）。接收数据选通延迟值的最终值和发送数据延迟值的最终值被训练（540）。使用接收数据选通延迟的工作值确定通过接收使能延迟值的右边缘（550）; 并且在通过的接收使能延迟值的左边缘和通过的接收使能延迟值的右边缘之间的中间的最终接收使能延迟值被设置（560）。

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