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1. 发明申请

US20130162357A1 OSCILLATOR WITH HIGHLY-ADJUSTABLE BANG-BANG CONTROL 有权
标题翻译：具有高度可调节的BANG-BANG控制的振荡器
公开(公告)号：US20130162357A1
公开(公告)日：2013-06-27
申请号：US13332990
申请日：2011-12-21
申请人： Bruce A. DOYLE , Emerson S. FANG , Alvin L. LOKE , Shawn SEARLES , Stephen F. GREENWOOD
发明人： Bruce A. DOYLE , Emerson S. FANG , Alvin L. LOKE , Shawn SEARLES , Stephen F. GREENWOOD
IPC分类号： H03K3/03
CPC分类号： H03L7/0807 , H03K3/0322 , H03L7/087 , H03L7/0995
摘要： A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.
摘要翻译：器件可以包括基于第一和第二控制信号产生时钟信号的振荡器。振荡器可以包括第一缓冲级，第二缓冲级。第一缓冲级可以输出基于第二缓冲级和第一控制信号的输出的第一信号。第二缓冲级可以输出时钟信号。时钟信号可以基于第一信号和第二控制信号。

2. 发明授权

US08319579B2 Passive filter and AC coupler receiver interface 有权
标题翻译：无源滤波器和交流耦合器接收器接口
公开(公告)号：US08319579B2
公开(公告)日：2012-11-27
申请号：US12955040
申请日：2010-11-29
申请人： Jingcheng Zhuang , Bruce A. Doyle , Emerson S. Fang
发明人： Jingcheng Zhuang , Bruce A. Doyle , Emerson S. Fang
IPC分类号： H04B3/04
CPC分类号： H04B3/14 , H04L25/0272 , H04L25/0292 , H04L25/03878
摘要： An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.
摘要翻译：一种装置包括耦合在响应于接收输入信号的第一节点和第二节点之间的电容器。该装置包括耦合到第二节点和第三节点的第一电路。第一电路可选择性地操作以分别配置均衡器的低频增益和均衡器的极点中的至少一个。均衡器包括第一电路和电容器。第二节点响应于在装置的第一模式中接收输入信号的AC信号的均衡版本。第二节点响应于在设备的第二模式中接收输入信号的AC信号的非均衡版本。输入信号的AC信号的均衡版本可以是装置的第一模式中的AC信号的电平移位和均衡版本。

3. 发明授权

US5031152A Test circuit for non-volatile storage cell 失效
标题翻译：用于非易失性存储单元的测试电路
公开(公告)号：US5031152A
公开(公告)日：1991-07-09
申请号：US414775
申请日：1989-09-29
申请人： Bruce A. Doyle
发明人： Bruce A. Doyle
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3185 , G11C29/24 , G11C29/52
CPC分类号： G11C29/24 , G01R31/318516 , G11C29/52
摘要： A latch is provided in association with each non-volatile memory element used to store configuration information on a programmable logic device. In normal use, configuration information is written to the non-volatile memory elements in the usual manner. However, during testing volatile memory elements in the usual manner. However, during testing configuration information is written only to the latches associated with the non-volatile elements. The latches place the data stored therein onto the same architecture bit line used by the non-volatile memory elements, allowing chip configuration testing to be performed without actually writing to the non-volatile memory elements. The latches can be written to at a much faster speed than the non-volatile memory elements can be programmed, greatly decreasing the time needed for full testing of the programmable logic device.

4. 发明授权

US08542068B2 Oscillator with highly-adjustable bang-bang control 有权
标题翻译：振荡器具有高度可调的爆炸控制
公开(公告)号：US08542068B2
公开(公告)日：2013-09-24
申请号：US13332990
申请日：2011-12-21
申请人： Bruce A. Doyle , Emerson S. Fang , Alvin L. Loke , Shawn Searles , Stephen F. Greenwood
发明人： Bruce A. Doyle , Emerson S. Fang , Alvin L. Loke , Shawn Searles , Stephen F. Greenwood
IPC分类号： H03L7/00
CPC分类号： H03L7/0807 , H03K3/0322 , H03L7/087 , H03L7/0995
摘要： A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.
摘要翻译：器件可以包括基于第一和第二控制信号产生时钟信号的振荡器。振荡器可以包括第一缓冲级，第二缓冲级。第一缓冲级可以输出基于第二缓冲级和第一控制信号的输出的第一信号。第二缓冲级可以输出时钟信号。时钟信号可以基于第一信号和第二控制信号。

5. 发明申请

US20130162310A1 CLOCK GENERATOR WITH INTEGRATED PHASE OFFSET PROGRAMMABILITY 有权
标题翻译：具有集成相位偏移可编程性的时钟发生器
公开(公告)号：US20130162310A1
公开(公告)日：2013-06-27
申请号：US13333011
申请日：2011-12-21
申请人： Bruce A. DOYLE , Emerson S. FANG , Alvin L. LOKE , Shawn SEARLES , Stephen F. GREENWOOD
发明人： Bruce A. DOYLE , Emerson S. FANG , Alvin L. LOKE , Shawn SEARLES , Stephen F. GREENWOOD
IPC分类号： H03L7/08 , H03K17/00
CPC分类号： H03K3/0322 , H03L7/0996
摘要： A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.
摘要翻译：装置可以包括第一，第二和第三缓冲级。该装置还可以包括选择器电路，用于选择性地输出第二缓冲级的输出或第三缓冲级的输出之一。器件可以包括输出以提供第一时钟信号，其中第一时钟信号是第一缓冲器级的输出，并且器件还包括输出以提供第二时钟信号，其中第二时钟信号是选择器电路。

6. 发明申请

US20120133459A1 PASSIVE FILTER AND AC COUPLER RECEIVER INTERFACE 有权
标题翻译：被动过滤器和交流耦合器接收器接口
公开(公告)号：US20120133459A1
公开(公告)日：2012-05-31
申请号：US12955040
申请日：2010-11-29
申请人： Jingcheng Zhuang , Bruce A. Doyle , Emerson S. Fang
发明人： Jingcheng Zhuang , Bruce A. Doyle , Emerson S. Fang
IPC分类号： H04B3/14
CPC分类号： H04B3/14 , H04L25/0272 , H04L25/0292 , H04L25/03878
摘要： An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.
摘要翻译：一种装置包括耦合在响应于接收输入信号的第一节点和第二节点之间的电容器。该装置包括耦合到第二节点和第三节点的第一电路。第一电路可选择性地操作以分别配置均衡器的低频增益和均衡器的极点中的至少一个。均衡器包括第一电路和电容器。第二节点响应于在装置的第一模式中接收输入信号的AC信号的均衡版本。第二节点响应于在设备的第二模式中接收输入信号的AC信号的非均衡版本。输入信号的AC信号的均衡版本可以是装置的第一模式中的AC信号的电平移位和均衡版本。

7. 发明授权

US08729944B2 Clock generator with integrated phase offset programmability 有权
标题翻译：具有集成相位偏移可编程性的时钟发生器
公开(公告)号：US08729944B2
公开(公告)日：2014-05-20
申请号：US13333011
申请日：2011-12-21
申请人： Bruce A. Doyle , Emerson S. Fang , Alvin L. Loke , Shawn Searles , Stephen F. Greenwood
发明人： Bruce A. Doyle , Emerson S. Fang , Alvin L. Loke , Shawn Searles , Stephen F. Greenwood
IPC分类号： H03K5/13
CPC分类号： H03K3/0322 , H03L7/0996
摘要： A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.
摘要翻译：装置可以包括第一，第二和第三缓冲级。该装置还可以包括选择器电路，用于选择性地输出第二缓冲级的输出或第三缓冲级的输出之一。器件可以包括输出以提供第一时钟信号，其中第一时钟信号是第一缓冲器级的输出，并且器件还包括输出以提供第二时钟信号，其中第二时钟信号是选择器电路。

8. 发明授权

US5170373A Three transistor EEPROM cell 失效
标题翻译：三个晶体管EEPROM单元
公开(公告)号：US5170373A
公开(公告)日：1992-12-08
申请号：US429308
申请日：1989-10-31
申请人： Bruce A. Doyle , Randy C. Steele , Safoin A. Raad
发明人： Bruce A. Doyle , Randy C. Steele , Safoin A. Raad
IPC分类号： G11C17/00 , G11C16/04 , H01L27/115 , H03K19/177
CPC分类号： G11C16/0433 , H01L27/115
摘要： An EEPROM cell suitable for use in programmable logic devices contains three transistors. A floating gate transistor is used to retain a programmed value using charge storage on the floating gate. A read transistor is connected between the floating gate transistor and an output signal line, and used to access the value stored in the floating gate transistor. A write transistor is connected to the floating gate transistor opposite the read transistor, and is used when programming the floating gate transistor. The write transistor and its associated control circuitry are fabricated to handle the higher programming voltages required by the floating gate device. The read transistor and associated drive circuitry are not required to handle the higher programming voltages, and can be fabricated using smaller, faster devices.

9. 发明授权

US5159599A High speed testing for programmable logic devices 失效
标题翻译：用于可编程逻辑器件的高速测试
公开(公告)号：US5159599A
公开(公告)日：1992-10-27
申请号：US560383
申请日：1990-07-31
申请人： Randy C. Steele , Bruce A. Doyle
发明人： Randy C. Steele , Bruce A. Doyle
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/10 , H03K19/173 , H03K19/177
CPC分类号： G01R31/318516
摘要： A shift register used to shift programming and test data into a programmable logic device is modified so that each bit thereof can be directly set or reset. Control signals can be used to directly place the required test patterns into the shift register. A memory connected to the shift register, and associated logic, provides a means for testing whether data was accurately written to the array without shifting any data off of the device.

10. 发明申请

US20140049292A1 INTEGRATED CIRCUIT PACKAGE HAVING MEDIUM-INDEPENDENT SIGNALING INTERFACE COUPLED TO CONNECTOR ASSEMBLY 审中-公开
标题翻译：具有中型独立信号接口的集成电路封装与连接器总成相连
公开(公告)号：US20140049292A1
公开(公告)日：2014-02-20
申请号：US13588704
申请日：2012-08-17
申请人： Petre Popescu , Emerson S. Fang , Bruce A. Doyle , Alvin Leng Sun Loke , Shawn Searles
发明人： Petre Popescu , Emerson S. Fang , Bruce A. Doyle , Alvin Leng Sun Loke , Shawn Searles
IPC分类号： H01R12/70 , G02B6/36 , H03K5/01
CPC分类号： G02B6/43 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/48227 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/12043 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/014 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.
摘要翻译：集成电路（IC）封装包括设置在IC封装的第一表面处的电触点，实现电信令接口的集成电路以及可在IC封装的第二表面处接近的连接器组件。连接器组件将机械地连接到另一个连接器组件，并且包括电耦合到电信令接口的接触端子。连接器组件可以被配置为提供与另一连接器组件的摩擦联接，以允许另一连接器组件可移除地附接。一种系统包括IC封装和具有机械连接到IC封装的连接器组件的连接器组件的外部收发器模块。电信令接口根据一种信号格式与外部收发器模块进行信号通信，而外部收发器模块根据另一信号格式通过传输介质进行信令传输。

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