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1. 发明申请

US20120066445A1 DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES 有权
标题翻译：具有可配置电源状态的动态RAM PHY接口
公开(公告)号：US20120066445A1
公开(公告)日：2012-03-15
申请号：US12910412
申请日：2010-10-22
申请人： Shawn Searles , Nicholas T. Humphries , Brian W. Amick , Richard W. Reeves , Hanwoo Cho , Ronald L. Pettyjohn
发明人： Shawn Searles , Nicholas T. Humphries , Brian W. Amick , Richard W. Reeves , Hanwoo Cho , Ronald L. Pettyjohn
IPC分类号： G06F12/00 , G11C5/14 , G11C7/22
CPC分类号： G06F12/00 , G06F1/3275 , G06F13/1689 , G06F13/4072 , G06F13/4086 , Y02D10/14
摘要： A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.
摘要翻译：公开了物理存储器接口（Phy）和操作方法。 Phy接口包括被配置为接收第一功率上下文和第二功率上下文的命令和状态寄存器（CSR）。选择电路被配置为在第一和第二电源上下文之间切换。提供了多个可调延迟元件，每个延迟元件具有响应于所选功率上下文的延迟时间。配置的第一组CSR可以存储第一功率上下文，并且配置的第二组CSR可以存储第二功率上下文。 Phy接口还可以包括多个驱动器，每个驱动器响应于所选择的功率上下文具有可选择的驱动强度。 Phy接口还可以包括多个接收器，每个接收器具有响应于所选择的功率上下文的可选择的终端阻抗。在功率上下文之间切换可导致延迟元件的调整，一个或多个驱动器/接收器的驱动强度和/或终端阻抗。

2. 发明授权

US08356155B2 Dynamic RAM Phy interface with configurable power states 有权
标题翻译：动态RAM Phy接口具有可配置的电源状态
公开(公告)号：US08356155B2
公开(公告)日：2013-01-15
申请号：US12910412
申请日：2010-10-22
申请人： Shawn Searles , Nicholas T. Humphries , Brian W. Amick , Richard W. Reeves , Hanwoo Cho , Ronald L. Pettyjohn
发明人： Shawn Searles , Nicholas T. Humphries , Brian W. Amick , Richard W. Reeves , Hanwoo Cho , Ronald L. Pettyjohn
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F1/3275 , G06F13/1689 , G06F13/4072 , G06F13/4086 , Y02D10/14
摘要： A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.
摘要翻译：公开了物理存储器接口（Phy）和操作方法。 Phy接口包括被配置为接收第一功率上下文和第二功率上下文的命令和状态寄存器（CSR）。选择电路被配置为在第一和第二电源上下文之间切换。提供了多个可调延迟元件，每个延迟元件具有响应于所选功率上下文的延迟时间。配置的第一组CSR可以存储第一功率上下文，并且配置的第二组CSR可以存储第二功率上下文。 Phy接口还可以包括多个驱动器，每个驱动器响应于所选择的功率上下文具有可选择的驱动强度。 Phy接口还可以包括多个接收器，每个接收器具有响应于所选择的功率上下文的可选择的终端阻抗。在功率上下文之间切换可导致延迟元件的调整，一个或多个驱动器/接收器的驱动强度和/或终端阻抗。

3. 发明授权

US08373447B2 Method and apparatus of alternating service modes of an SOI process circuit 有权
标题翻译： SOI工艺电路交替工作模式的方法和装置
公开(公告)号：US08373447B2
公开(公告)日：2013-02-12
申请号：US12953593
申请日：2010-11-24
申请人： Joseph E. Kidd , Brian W. Amick , Ryan J. Hensley , James R. Magro , Ronald L. Pettyjohn
发明人： Joseph E. Kidd , Brian W. Amick , Ryan J. Hensley , James R. Magro , Ronald L. Pettyjohn
IPC分类号： H03K17/00 , G06F1/08
CPC分类号： G06F1/324 , Y02D10/126
摘要： A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.
摘要翻译：一种绝缘体上硅（SOI）工艺电路交替工作模式的方法和装置包括确定SOI工艺电路是处于第一还是第二工作模式。基于该确定，选择第一时钟或第二时钟沿着SOI处理电路的总线进行传输。通知该信号的接收装置是否在第一服务模式或第二服务模式中操作SOI处理电路。

4. 发明申请

US20120126871A1 METHOD AND APPARATUS OF ALTERNATING SERVICE MODES OF AN SOI PROCESS CIRCUIT 有权
标题翻译： SOI工艺电路替代服务模式的方法与装置
公开(公告)号：US20120126871A1
公开(公告)日：2012-05-24
申请号：US12953593
申请日：2010-11-24
申请人： Joseph E. Kidd , Brian W. Amick , Ryan J. Hensley , James R. Magro , Ronald L. Pettyjohn
发明人： Joseph E. Kidd , Brian W. Amick , Ryan J. Hensley , James R. Magro , Ronald L. Pettyjohn
IPC分类号： G06F1/04
CPC分类号： G06F1/324 , Y02D10/126
摘要： A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.
摘要翻译：一种绝缘体上硅（SOI）工艺电路交替工作模式的方法和装置包括确定SOI工艺电路是处于第一还是第二工作模式。基于该确定，选择第一时钟或第二时钟沿着SOI处理电路的总线进行传输。通知该信号的接收装置是否在第一服务模式或第二服务模式中操作SOI处理电路。

5. 发明授权

US06526062B1 System and method for scheduling and rescheduling the transmission of cell objects of different traffic types 有权
标题翻译：用于调度和重新安排不同业务类型的小区对象的传输的系统和方法
公开(公告)号：US06526062B1
公开(公告)日：2003-02-25
申请号：US09170609
申请日：1998-10-13
申请人： Walter C. Milliken , Steven Kohalmi , Philip P. Carvey , Ronald L. Pettyjohn , Stanley P. Sassower , Craig Partridge
发明人： Walter C. Milliken , Steven Kohalmi , Philip P. Carvey , Ronald L. Pettyjohn , Stanley P. Sassower , Craig Partridge
IPC分类号： H04L1228
CPC分类号： H04L47/562 , H04L47/50
摘要： A computer system for transmitting packets includes a manager and scheduling elements for managing the transmission of the packets over one or more logical channels. The computer system can prioritize the transmission of packets based on the type of traffic and maintain quality of service (QoS) characteristics associated with a logical channel. In addition, the computer system can execute a threading process to ensure the efficient and timely transmission of certain types of packets without using any complex mathematical operations.
摘要翻译：用于发送分组的计算机系统包括管理器和用于管理通过一个或多个逻辑信道的分组传输的调度元素。计算机系统可以基于业务类型对分组的传输进行优先级排序，并且保持与逻辑信道相关联的服务质量（QoS）特性。此外，计算机系统可以执行线程处理，以确保某些类型的分组的有效和及时传输，而不需要使用任何复杂的数学运算。

6. 发明授权

US07418523B2 Operation of a multiplicity of time sorted queues with reduced memory 有权
标题翻译：运行多个时间排序队列，减少内存
公开(公告)号：US07418523B2
公开(公告)日：2008-08-26
申请号：US10056609
申请日：2002-01-24
申请人： Ronald L. Pettyjohn , Walter C. Milliken
发明人： Ronald L. Pettyjohn , Walter C. Milliken
IPC分类号： G06F15/16 , G06F11/00
CPC分类号： H04L47/22 , H04L47/28 , H04L47/50 , H04L47/562 , H04L47/564 , H04L49/30 , H04L49/3027 , H04L49/3081 , H04L2012/5649 , H04L2012/5679 , H04L2012/568 , H04L2012/5681
摘要： A technique for controlling a multiplicity of time-sorted queues with a single controller and supporting memory, which may be software-configured so as to allow the use of the controller in an implementation having a multiplicity and variety of output lines or channels. The technique includes receiving a plurality of packets from one or more packet flows at a respective time-based output port queue of the network switch, in which each packet has a timestamp associated therewith. Each output card memory can be divided into a plurality of queues, in which the number of queues corresponds to the number of flows received by the switch and the size of each queue is proportional to the fractional amount of the total bandwidth of the switch used by the corresponding packet flow.
摘要翻译：一种用于利用单个控制器和支持存储器来控制多个时间排序队列的技术，其可以被软件配置为允许在具有多种和多种输出线或通道的实现中使用控制器。该技术包括在网络交换机的相应的基于时间的输出端口队列处从一个或多个分组流接收多个分组，其中每个分组具有与其相关联的时间戳。每个输出卡存储器可以被划分成多个队列，其中队列数量对应于由交换机接收的流量的数量，并且每个队列的大小与由所使用的交换机使用的总带宽的分数量成比例相应的数据包流。

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