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1. 发明授权

US08356155B2 Dynamic RAM Phy interface with configurable power states 有权
标题翻译：动态RAM Phy接口具有可配置的电源状态
公开(公告)号：US08356155B2
公开(公告)日：2013-01-15
申请号：US12910412
申请日：2010-10-22
申请人： Shawn Searles , Nicholas T. Humphries , Brian W. Amick , Richard W. Reeves , Hanwoo Cho , Ronald L. Pettyjohn
发明人： Shawn Searles , Nicholas T. Humphries , Brian W. Amick , Richard W. Reeves , Hanwoo Cho , Ronald L. Pettyjohn
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F1/3275 , G06F13/1689 , G06F13/4072 , G06F13/4086 , Y02D10/14
摘要： A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.
摘要翻译：公开了物理存储器接口（Phy）和操作方法。 Phy接口包括被配置为接收第一功率上下文和第二功率上下文的命令和状态寄存器（CSR）。选择电路被配置为在第一和第二电源上下文之间切换。提供了多个可调延迟元件，每个延迟元件具有响应于所选功率上下文的延迟时间。配置的第一组CSR可以存储第一功率上下文，并且配置的第二组CSR可以存储第二功率上下文。 Phy接口还可以包括多个驱动器，每个驱动器响应于所选择的功率上下文具有可选择的驱动强度。 Phy接口还可以包括多个接收器，每个接收器具有响应于所选择的功率上下文的可选择的终端阻抗。在功率上下文之间切换可导致延迟元件的调整，一个或多个驱动器/接收器的驱动强度和/或终端阻抗。

2. 发明申请

US20120066445A1 DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES 有权
标题翻译：具有可配置电源状态的动态RAM PHY接口
公开(公告)号：US20120066445A1
公开(公告)日：2012-03-15
申请号：US12910412
申请日：2010-10-22
申请人： Shawn Searles , Nicholas T. Humphries , Brian W. Amick , Richard W. Reeves , Hanwoo Cho , Ronald L. Pettyjohn
发明人： Shawn Searles , Nicholas T. Humphries , Brian W. Amick , Richard W. Reeves , Hanwoo Cho , Ronald L. Pettyjohn
IPC分类号： G06F12/00 , G11C5/14 , G11C7/22
CPC分类号： G06F12/00 , G06F1/3275 , G06F13/1689 , G06F13/4072 , G06F13/4086 , Y02D10/14
摘要： A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.
摘要翻译：公开了物理存储器接口（Phy）和操作方法。 Phy接口包括被配置为接收第一功率上下文和第二功率上下文的命令和状态寄存器（CSR）。选择电路被配置为在第一和第二电源上下文之间切换。提供了多个可调延迟元件，每个延迟元件具有响应于所选功率上下文的延迟时间。配置的第一组CSR可以存储第一功率上下文，并且配置的第二组CSR可以存储第二功率上下文。 Phy接口还可以包括多个驱动器，每个驱动器响应于所选择的功率上下文具有可选择的驱动强度。 Phy接口还可以包括多个接收器，每个接收器具有响应于所选择的功率上下文的可选择的终端阻抗。在功率上下文之间切换可导致延迟元件的调整，一个或多个驱动器/接收器的驱动强度和/或终端阻抗。

3. 发明授权

US07929361B2 Circuit using a shared delay locked loop (DLL) and method therefor 有权
标题翻译：电路使用共享延迟锁定环（DLL）及其方法
公开(公告)号：US07929361B2
公开(公告)日：2011-04-19
申请号：US12059613
申请日：2008-03-31
申请人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
发明人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit (340) has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller (210) enables the shared DLL (360) for use by the receive circuit (320) during a receive cycle, and enables the shared DLL (360) for use by the transmit circuit (340) during a transmit cycle.
摘要翻译：收发器（222）包括接收电路（320），发射电路（340），共享延迟锁定环（DLL）（360）和控制器（210）。接收电路（320）具有耦合到外部数据终端的第一输入，耦合到外部数据选通端的第二输入和耦合到内部数据终端的输出。发射电路（340）具有耦合到内部数据终端的第一输入端，用于接收内部时钟信号的第二输入端，耦合到外部数据端子的第一输出端和耦合到外部数据选通端子的第二输出端。控制器（210）使得共享DLL（360）能够在接收周期期间由接收电路（320）使用，并且使得共享DLL（360）能够在发送周期期间由发送电路（340）使用。

4. 发明授权

US07872937B2 Data driver circuit for a dynamic random access memory (DRAM) controller or the like and method therefor 有权
标题翻译：用于动态随机存取存储器（DRAM）控制器等的数据驱动器电路及其方法
公开(公告)号：US07872937B2
公开(公告)日：2011-01-18
申请号：US12059641
申请日：2008-03-31
申请人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
发明人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
IPC分类号： G11C8/00
CPC分类号： G06F13/1689
摘要： A data driver includes a first latch (322), an extension logic circuit (324), and a second latch (330). The first latch (322) has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit (324) has an input coupled to the output of the first latch (322), a control input for receiving a control signal, and an output. The extension logic circuit (324) selectively delays the output of the first latch (322) in response to the control signal. The second latch (330) has an input coupled to the output of the extension logic circuit (324), a clock input for receiving a second clock signal, and an output for providing an output data signal.
摘要翻译：数据驱动器包括第一锁存器（322），扩展逻辑电路（324）和第二锁存器（330）。第一锁存器（322）具有用于接收输入数据信号的输入端，用于接收第一时钟信号的时钟输入端和输出端。扩展逻辑电路（324）具有耦合到第一锁存器（322）的输出的输入端，用于接收控制信号的控制输入端和输出端。扩展逻辑电路（324）响应于控制信号有选择地延迟第一锁存器（322）的输出。第二锁存器（330）具有耦合到扩展逻辑电路（324）的输出的输入，用于接收第二时钟信号的时钟输入和用于提供输出数据信号的输出。

5. 发明授权

US07869287B2 Circuit for locking a delay locked loop (DLL) and method therefor 有权
标题翻译：用于锁定延迟锁定环（DLL）的电路及其方法
公开(公告)号：US07869287B2
公开(公告)日：2011-01-11
申请号：US12059593
申请日：2008-03-31
申请人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
发明人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： A receive circuit (320) includes a DLL core (510), a latch (326), and a DLL control circuit (520). The DLL core (510) has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch (326) has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core (510), and an output for providing an internal data signal. The DLL control circuit (520) provides the DLL clock signal to the first input of the DLL core (510) responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core (510) responsive to a processor clock signal while the receive circuit (320) is in a second mode.
摘要翻译：接收电路（320）包括DLL核心（510），锁存器（326）和DLL控制电路（520）。 DLL核心（510）具有用于接收DLL时钟信号的第一输入端，用于接收延迟线选择信号的第二输入端和用于提供延迟数据选通信号的输出端。锁存器（326）具有用于接收外部数据信号的信号输入，耦合到DLL核心（510）的输出的控制输入和用于提供内部数据信号的输出。当接收电路处于第一模式时，DLL控制电路（520）响应于存储器数据选通信号而将DLL时钟信号提供给DLL核心（510）的第一输入端，并且将DLL时钟信号提供给第一输入所述DLL核心（510）响应于所述接收电路（320）处于第二模式时的处理器时钟信号。

6. 发明申请

US20090245010A1 Data Driver Circuit for a Dynamic Random Access Memory (DRAM) Controller or the Like and Method Therefor 有权
标题翻译：用于动态随机存取存储器（DRAM）控制器等的数据驱动器电路及其方法
公开(公告)号：US20090245010A1
公开(公告)日：2009-10-01
申请号：US12059641
申请日：2008-03-31
申请人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
发明人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
IPC分类号： G11C8/08
CPC分类号： G06F13/1689
摘要： A data driver includes a first latch (322), an extension logic circuit (324), and a second latch (330). The first latch (322) has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit (324) has an input coupled to the output of the first latch (322), a control input for receiving a control signal, and an output. The extension logic circuit (324) selectively delays the output of the first latch (322) in response to the control signal. The second latch (330) has an input coupled to the output of the extension logic circuit (324), a clock input for receiving a second clock signal, and an output for providing an output data signal.
摘要翻译：数据驱动器包括第一锁存器（322），扩展逻辑电路（324）和第二锁存器（330）。第一锁存器（322）具有用于接收输入数据信号的输入端，用于接收第一时钟信号的时钟输入端和输出端。扩展逻辑电路（324）具有耦合到第一锁存器（322）的输出的输入端，用于接收控制信号的控制输入端和输出端。扩展逻辑电路（324）响应于控制信号有选择地延迟第一锁存器（322）的输出。第二锁存器（330）具有耦合到扩展逻辑电路（324）的输出的输入，用于接收第二时钟信号的时钟输入和用于提供输出数据信号的输出。

7. 发明申请

US20090244996A1 Circuit Using a Shared Delay Locked Loop (DLL) and Method Therefor 有权
标题翻译：使用共享延迟锁定环路（DLL）的电路及其方法
公开(公告)号：US20090244996A1
公开(公告)日：2009-10-01
申请号：US12059613
申请日：2008-03-31
申请人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
发明人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
IPC分类号： G11C7/22
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit (340) has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller (210) enables the shared DLL (360) for use by the receive circuit (320) during a receive cycle, and enables the shared DLL (360) for use by the transmit circuit (340) during a transmit cycle.
摘要翻译：收发器（222）包括接收电路（320），发射电路（340），共享延迟锁定环（DLL）（360）和控制器（210）。接收电路（320）具有耦合到外部数据终端的第一输入，耦合到外部数据选通端的第二输入和耦合到内部数据终端的输出。发射电路（340）具有耦合到内部数据终端的第一输入端，用于接收内部时钟信号的第二输入端，耦合到外部数据端子的第一输出端和耦合到外部数据选通端子的第二输出端。控制器（210）使得共享DLL（360）能够在接收周期期间由接收电路（320）使用，并且使得共享DLL（360）能够在发送周期期间由发送电路（340）使用。

8. 发明申请

US20090244995A1 Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor 有权
标题翻译：用于锁定延迟锁定环路（DLL）的电路及其方法
公开(公告)号：US20090244995A1
公开(公告)日：2009-10-01
申请号：US12059593
申请日：2008-03-31
申请人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
发明人： Shawn Searles , Faisal A. Syed , Nicholas T. Humphries
IPC分类号： G11C7/22
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： A receive circuit (320) includes a DLL core (510), a latch (326), and a DLL control circuit (520). The DLL core (510) has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch (326) has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core (510), and an output for providing an internal data signal. The DLL control circuit (520) provides the DLL clock signal to the first input of the DLL core (510) responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core (510) responsive to a processor clock signal while the receive circuit (320) is in a second mode.
摘要翻译：接收电路（320）包括DLL核心（510），锁存器（326）和DLL控制电路（520）。 DLL核心（510）具有用于接收DLL时钟信号的第一输入端，用于接收延迟线选择信号的第二输入端和用于提供延迟数据选通信号的输出端。锁存器（326）具有用于接收外部数据信号的信号输入，耦合到DLL核心（510）的输出的控制输入和用于提供内部数据信号的输出。当接收电路处于第一模式时，DLL控制电路（520）响应于存储器数据选通信号而将DLL时钟信号提供给DLL核心（510）的第一输入端，并且将DLL时钟信号提供给第一输入所述DLL核心（510）响应于所述接收电路（320）处于第二模式时的处理器时钟信号。

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