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1. 发明授权

US09330979B2 LDMOS transistor having elevated field oxide bumps and method of making same 有权
标题翻译：具有升高的场氧化物凸块的LDMOS晶体管及其制造方法
公开(公告)号：US09330979B2
公开(公告)日：2016-05-03
申请号：US12260806
申请日：2008-10-29
申请人： Sharon Levin , Alexey Heiman , Zohar Shaked , Gal Fleishon
发明人： Sharon Levin , Alexey Heiman , Zohar Shaked , Gal Fleishon
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/423 , H01L29/66 , H01L29/78 , H01L21/265 , H01L29/08 , H01L29/40
CPC分类号： H01L21/823462 , H01L21/26586 , H01L21/823418 , H01L21/823814 , H01L21/823857 , H01L29/086 , H01L29/402 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A low Rdson LDMOS transistor having a shallow field oxide region that separates a gate electrode of the transistor from a drain diffusion region of the transistor. The shallow field oxide region is formed separate from the field isolation regions (e.g., STI regions) used to isolate circuit elements on the substrate. Fabrication of the shallow field oxide region is controlled such that this region extends below the upper surface of the semiconductor substrate to a depth that is much shallower than the depth of field isolation regions. For example, the shallow field oxide region may extend below the upper surface of the substrate by only Angstroms or less. As a result, the current path through the resulting LDMOS transistor is substantially unimpeded by the shallow field oxide region, resulting in a low on-resistance.
摘要翻译：具有将晶体管的栅电极与晶体管的漏极扩散区分离的浅场氧化物区域的低Rdson LDMOS晶体管。浅场氧化物区域与用于隔离衬底上的电路元件的场隔离区域（例如，STI区域）分开形成。控制浅场氧化物区域的制造使得该区域在半导体衬底的上表面下方延伸到比景深隔离区域浅得多的深度。例如，浅场氧化物区域可以在衬底的上表面下方仅延伸一埃以下。结果，通过所产生的LDMOS晶体管的电流路径基本上不受浅场氧化物区域的阻碍，导致低的导通电阻。

2. 发明申请

US20100102388A1 LDMOS Transistor Having Elevated Field Oxide Bumps And Method Of Making Same 有权
标题翻译：具有高场氧化物碰撞的LDMOS晶体管及其制造方法
公开(公告)号：US20100102388A1
公开(公告)日：2010-04-29
申请号：US12260806
申请日：2008-10-29
申请人： Sharon Levin , Alexey Heiman , Zohar Kuritsky , Gal Fleishon
发明人： Sharon Levin , Alexey Heiman , Zohar Kuritsky , Gal Fleishon
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823462 , H01L21/26586 , H01L21/823418 , H01L21/823814 , H01L21/823857 , H01L29/086 , H01L29/402 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A low Rdson LDMOS transistor having a shallow field oxide region that separates a gate electrode of the transistor from a drain diffusion region of the transistor. The shallow field oxide region is formed separate from the field isolation regions (e.g., STI regions) used to isolate circuit elements on the substrate. Fabrication of the shallow field oxide region is controlled such that this region extends below the upper surface of the semiconductor substrate to a depth that is much shallower than the depth of field isolation regions. For example, the shallow field oxide region may extend below the upper surface of the substrate by only Angstroms or less. As a result, the current path through the resulting LDMOS transistor is substantially unimpeded by the shallow field oxide region, resulting in a low on-resistance.
摘要翻译：具有将晶体管的栅电极与晶体管的漏极扩散区分离的浅场氧化物区域的低Rdson LDMOS晶体管。浅场氧化物区域与用于隔离衬底上的电路元件的场隔离区域（例如，STI区域）分开形成。控制浅场氧化物区域的制造使得该区域在半导体衬底的上表面下方延伸到比景深隔离区域浅得多的深度。例如，浅场氧化物区域可以在衬底的上表面下方仅延伸一埃以下。结果，通过所产生的LDMOS晶体管的电流路径基本上不受浅场氧化物区域的阻碍，导致低的导通电阻。

3. 发明授权

US07575977B2 Self-aligned LDMOS fabrication method integrated deep-sub-micron VLSI process, using a self-aligned lithography etches and implant process 有权
标题翻译：自对准LDMOS制造方法集成深亚微米VLSI工艺，使用自对准光刻蚀刻和注入工艺
公开(公告)号：US07575977B2
公开(公告)日：2009-08-18
申请号：US11691459
申请日：2007-03-26
申请人： Sharon Levin , Ira Naot , Alexei Heiman
发明人： Sharon Levin , Ira Naot , Alexei Heiman
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/26586 , H01L21/823807 , H01L21/823828 , H01L27/0922 , H01L29/0653 , H01L29/086 , H01L29/0869 , H01L29/665 , H01L29/66659 , H01L29/66689 , H01L29/7835
摘要： An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device.
摘要翻译：集成电路包括LDMOS器件和使用深亚微米VLSI制造工艺同时形成在衬底上的一个或多个低功率CMOS器件。使用双掩模蚀刻工艺对LDMOS多晶硅（多晶硅）栅极结构进行构图。第一蚀刻掩模用于限定远离深体/排出植入物的栅极结构的第一边缘。然后使用第二蚀刻掩模来限定栅极结构的第二边缘，并且随后形成深体/漏极植入物，第二蚀刻掩模然后被保持在栅极结构上。在深入植入后，形成浅的植入物和金属化以完成LDMOS器件。

4. 发明申请

US20130320443A1 Deep Silicon Via As A Drain Sinker In Integrated Vertical DMOS Transistor 有权
公开(公告)号：US20130320443A1
公开(公告)日：2013-12-05
申请号：US13484238
申请日：2012-05-30
申请人： Sharon Levin , Zachary K. Lee , Shye Shapira
发明人： Sharon Levin , Zachary K. Lee , Shye Shapira
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L29/7809 , H01L21/823487 , H01L21/82385 , H01L21/823857 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/41741 , H01L29/4916
摘要： A vertical DMOS device implements one or more deep silicon via (DSV) plugs, thereby significantly reducing the layout area and on-resistance (RDSON) of the device. The DSV plugs extend through a semiconductor substrate to contact a conductively doped buried diffusion region, which forms the drain of the vertical DMOS device. Methods for fabricating the vertical DMOS device are compatible with conventional sub-micron VLSI processes, such that the vertical DMOS device can be readily fabricated on the same integrated circuit as CMOS devices and analog devices, such as lateral double-diffused MOS (LDMOS) devices.

5. 发明申请

US20080242033A1 Self-Aligned LDMOS Fabrication Method Integrated Deep-Sub-Micron VLSI Process, Using A Self-Aligned Lithography Etches And Implant Process 有权
标题翻译：自对准LDMOS制造方法集成深亚微米VLSI工艺，使用自对准平版印刷刻蚀和植入工艺
公开(公告)号：US20080242033A1
公开(公告)日：2008-10-02
申请号：US11691459
申请日：2007-03-26
申请人： Sharon Levin , Ira Naot , Alexei Heiman
发明人： Sharon Levin , Ira Naot , Alexei Heiman
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/26586 , H01L21/823807 , H01L21/823828 , H01L27/0922 , H01L29/0653 , H01L29/086 , H01L29/0869 , H01L29/665 , H01L29/66659 , H01L29/66689 , H01L29/7835
摘要： An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device.
摘要翻译：集成电路包括LDMOS器件和使用深亚微米VLSI制造工艺同时形成在衬底上的一个或多个低功率CMOS器件。使用双掩模蚀刻工艺对LDMOS多晶硅（多晶硅）栅极结构进行构图。第一蚀刻掩模用于限定远离深体/排出植入物的栅极结构的第一边缘。然后使用第二蚀刻掩模来限定栅极结构的第二边缘，并且随后形成深体/漏极植入物，第二蚀刻掩模然后被保持在栅极结构上。在深入植入后，形成浅的植入物和金属化以完成LDMOS器件。

6. 发明申请

US20060125039A1 Low parasitic capacitance schottky diode 有权
标题翻译：低寄生电容肖特基二极管
公开(公告)号：US20060125039A1
公开(公告)日：2006-06-15
申请号：US11135846
申请日：2005-05-23
申请人： Sharon Levin , Shye Shapira , Ira Naot
发明人： Sharon Levin , Shye Shapira , Ira Naot
IPC分类号： H01L29/47 , H01L21/44
CPC分类号： H01L27/0629 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/872
摘要： A low parasitic capacitance Schottky diode including a lightly doped polycrystalline silicon island that is formed on a shallow trench isolation (STI) pad such that the polycrystalline silicon island is entirely isolated from an underlying silicon substrate by the STI pad. The resulting structure reduces leakage and capacitive coupling to the substrate. Silicide contact structures are attached to lightly-doped and heavily-doped regions of the polycrystalline silicon island to form the Schottky junction and Ohmic contact, respectively, and are connected by metal structures to other components formed on the silicon substrate. The STI pad, polycrystalline silicon island, and silicide/metal contacts are formed using a standard CMOS process flow to minimize cost. A bolometer detector is provided by measuring current through the diode in reverse bias. An array of such detectors comprises an infrared or optical image sensor.
摘要翻译：包括形成在浅沟槽隔离（STI）焊盘上的轻掺杂多晶硅岛的低寄生电容肖特基二极管，使得多晶硅岛通过STI焊盘与下面的硅衬底完全隔离。所得到的结构减少了泄漏和电容耦合到衬底。硅化物接触结构分别连接到多晶硅岛的轻掺杂和重掺杂区域以形成肖特基结和欧姆接触，并且通过金属结构连接到形成在硅衬底上的其它组分。使用标准CMOS工艺流程形成STI焊盘，多晶硅岛和硅化物/金属触点以最小化成本。通过以反向偏置测量通过二极管的电流来提供测辐射热计检测器。这种检测器的阵列包括红外或光学图像传感器。

7. 发明授权

US08921173B2 Deep silicon via as a drain sinker in integrated vertical DMOS transistor 有权
标题翻译：深硅通孔作为集成垂直DMOS晶体管的漏极沉降片
公开(公告)号：US08921173B2
公开(公告)日：2014-12-30
申请号：US13484238
申请日：2012-05-30
申请人： Sharon Levin , Zachary K. Lee , Shye Shapira
发明人： Sharon Levin , Zachary K. Lee , Shye Shapira
IPC分类号： H01L21/337
CPC分类号： H01L29/7809 , H01L21/823487 , H01L21/82385 , H01L21/823857 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/41741 , H01L29/4916
摘要： A vertical DMOS device implements one or more deep silicon via (DSV) plugs, thereby significantly reducing the layout area and on-resistance (RDSON) of the device. The DSV plugs extend through a semiconductor substrate to contact a conductively doped buried diffusion region, which forms the drain of the vertical DMOS device. Methods for fabricating the vertical DMOS device are compatible with conventional sub-micron VLSI processes, such that the vertical DMOS device can be readily fabricated on the same integrated circuit as CMOS devices and analog devices, such as lateral double-diffused MOS (LDMOS) devices.
摘要翻译：垂直DMOS器件实现了一个或多个深硅通孔（DSV）插头，从而显着减少了器件的布局面积和导通电阻（RDSON）。 DSV插头延伸穿过半导体衬底以接触形成垂直DMOS器件的漏极的导电掺杂掩埋扩散区域。用于制造垂直DMOS器件的方法与传统的亚微米VLSI工艺兼容，使得垂直DMOS器件可以容易地制造在与CMOS器件和模拟器件相同的集成电路上，例如横向双扩散MOS（LDMOS）器件。

8. 发明授权

US07368760B2 Low parasitic capacitance Schottky diode 有权
标题翻译：低寄生电容肖特基二极管
公开(公告)号：US07368760B2
公开(公告)日：2008-05-06
申请号：US11135846
申请日：2005-05-23
申请人： Sharon Levin , Shye Shapira , Ira Noat
发明人： Sharon Levin , Shye Shapira , Ira Noat
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/0629 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/872
摘要： A low parasitic capacitance Schottky diode including a lightly doped polycrystalline silicon island that is formed on a shallow trench isolation (STI) pad such that the polycrystalline silicon island is entirely isolated from an underlying silicon substrate by the STI pad. The resulting structure reduces leakage and capacitive coupling to the substrate. Silicide contact structures are attached to lightly-doped and heavily-doped regions of the polycrystalline silicon island to form the Schottky junction and Ohmic contact, respectively, and are connected by metal structures to other components formed on the silicon substrate. The STI pad, polycrystalline silicon island, and silicide/metal contacts are formed using a standard CMOS process flow to minimize cost. A bolometer detector is provided by measuring current through the diode in reverse bias. An array of such detectors comprises an infrared or optical image sensor.
摘要翻译：包括形成在浅沟槽隔离（STI）焊盘上的轻掺杂多晶硅岛的低寄生电容肖特基二极管，使得多晶硅岛通过STI焊盘与下面的硅衬底完全隔离。所得到的结构减少了泄漏和电容耦合到衬底。硅化物接触结构分别连接到多晶硅岛的轻掺杂和重掺杂区域以形成肖特基结和欧姆接触，并且通过金属结构连接到形成在硅衬底上的其它组分。使用标准CMOS工艺流程形成STI焊盘，多晶硅岛和硅化物/金属触点以最小化成本。通过以反向偏置测量通过二极管的电流来提供测辐射热计检测器。这种检测器的阵列包括红外或光学图像传感器。

9. 发明授权

US07544557B2 Gate defined Schottky diode 有权
标题翻译：门限定肖特基二极管
公开(公告)号：US07544557B2
公开(公告)日：2009-06-09
申请号：US11255627
申请日：2005-10-21
申请人： Sharon Levin , Shye Shapira , Ira Naot , Robert J. Strain , Yossi Netzer
发明人： Sharon Levin , Shye Shapira , Ira Naot , Robert J. Strain , Yossi Netzer
IPC分类号： H01L21/8238
CPC分类号： H01L29/872 , H01L27/0814 , H01L27/095
摘要： A Schottky diode exhibiting low series resistance is efficiently fabricated using a substantially standard CMOS process flow by forming the Schottky diode using substantially the same structures and processes that are used to form a field effect transistor (FET) of a CMOS IC device. Polycrystalline silicon, which is used to form the gate structure of the FET, is utilized to form an isolation structure between the Schottky barrier and backside structure of the Schottky diode. Silicide (e.g., cobalt silicide (CoSi2)) structures, which are utilized to form source and drain metal-to-silicon contacts in the FET, are used to form the Schottky barrier and backside Ohmic contact of the Schottky diode. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.
摘要翻译：使用与用于形成CMOS IC器件的场效应晶体管（FET）的基本相同的结构和工艺，通过形成肖特基二极管，通过使用基本上标准的CMOS工艺流程，有效地制造了具有低串联电阻的肖特基二极管。用于形成FET的栅极结构的多晶硅用于在肖特基势垒和肖特基二极管的背侧结构之间形成隔离结构。用于在FET中形成源极和漏极金属 - 硅触点的硅化物（例如，硅化钴（CoSi 2））结构被用于形成肖特基势垒和肖特基二极管的背面欧姆接触。用于形成FET的源极和漏极扩散的重掺杂漏极（HDD）扩散和轻掺杂漏极（LDD）扩散被用于在背侧接触硅化物下形成合适的接触扩散。

10. 发明授权

US07485941B2 Cobalt silicide schottky diode on isolated well 有权
标题翻译：隔离好的硅化硅肖特基二极管
公开(公告)号：US07485941B2
公开(公告)日：2009-02-03
申请号：US11255338
申请日：2005-10-21
申请人： Sharon Levin , Shye Shapira , Ira Naot , Robert J. Strain , Yossi Netzer
发明人： Sharon Levin , Shye Shapira , Ira Naot , Robert J. Strain , Yossi Netzer
IPC分类号： H01L29/47
CPC分类号： H01L29/872 , H01L27/0629 , H01L27/0814 , H01L27/095
摘要： A Schottky diode is formed on an isolated well (e.g., a P-well formed in a buried N-well), and utilizes cobalt silicide (CoSi2) structures respectively formed on heavily doped and lightly doped regions of the isolated well to provide the Schottky barrier and backside (ohmic) contact structures of the Schottky diode. The surrounding buried N-well is coupled to a bias voltage. The Schottky barrier and backside contact structures are separated by isolation structures formed using polycrystalline silicon, which is used to form the gate structure of CMOS FETs, in order to minimize forward resistance. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.
摘要翻译：肖特基二极管形成在隔离阱（例如，在掩埋的N阱中形成的P阱）中，并且利用分离形成在隔离阱的重掺杂和轻掺杂区域上的硅化钴（CoSi 2）结构，以提供肖特基屏蔽和背面（欧姆）接触结构。周围埋置的N阱耦合到偏置电压。肖特基势垒和背面接触结构由使用多晶硅形成的隔离结构分开，其用于形成CMOS FET的栅极结构，以便使正向电阻最小化。用于形成FET的源极和漏极扩散的重掺杂漏极（HDD）扩散和轻掺杂漏极（LDD）扩散被用于在背侧接触硅化物下形成合适的接触扩散。

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