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1. 发明申请

US20080242033A1 Self-Aligned LDMOS Fabrication Method Integrated Deep-Sub-Micron VLSI Process, Using A Self-Aligned Lithography Etches And Implant Process 有权
标题翻译：自对准LDMOS制造方法集成深亚微米VLSI工艺，使用自对准平版印刷刻蚀和植入工艺
公开(公告)号：US20080242033A1
公开(公告)日：2008-10-02
申请号：US11691459
申请日：2007-03-26
申请人： Sharon Levin , Ira Naot , Alexei Heiman
发明人： Sharon Levin , Ira Naot , Alexei Heiman
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/26586 , H01L21/823807 , H01L21/823828 , H01L27/0922 , H01L29/0653 , H01L29/086 , H01L29/0869 , H01L29/665 , H01L29/66659 , H01L29/66689 , H01L29/7835
摘要： An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device.
摘要翻译：集成电路包括LDMOS器件和使用深亚微米VLSI制造工艺同时形成在衬底上的一个或多个低功率CMOS器件。使用双掩模蚀刻工艺对LDMOS多晶硅（多晶硅）栅极结构进行构图。第一蚀刻掩模用于限定远离深体/排出植入物的栅极结构的第一边缘。然后使用第二蚀刻掩模来限定栅极结构的第二边缘，并且随后形成深体/漏极植入物，第二蚀刻掩模然后被保持在栅极结构上。在深入植入后，形成浅的植入物和金属化以完成LDMOS器件。

2. 发明申请

US20060125039A1 Low parasitic capacitance schottky diode 有权
标题翻译：低寄生电容肖特基二极管
公开(公告)号：US20060125039A1
公开(公告)日：2006-06-15
申请号：US11135846
申请日：2005-05-23
申请人： Sharon Levin , Shye Shapira , Ira Naot
发明人： Sharon Levin , Shye Shapira , Ira Naot
IPC分类号： H01L29/47 , H01L21/44
CPC分类号： H01L27/0629 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/872
摘要： A low parasitic capacitance Schottky diode including a lightly doped polycrystalline silicon island that is formed on a shallow trench isolation (STI) pad such that the polycrystalline silicon island is entirely isolated from an underlying silicon substrate by the STI pad. The resulting structure reduces leakage and capacitive coupling to the substrate. Silicide contact structures are attached to lightly-doped and heavily-doped regions of the polycrystalline silicon island to form the Schottky junction and Ohmic contact, respectively, and are connected by metal structures to other components formed on the silicon substrate. The STI pad, polycrystalline silicon island, and silicide/metal contacts are formed using a standard CMOS process flow to minimize cost. A bolometer detector is provided by measuring current through the diode in reverse bias. An array of such detectors comprises an infrared or optical image sensor.
摘要翻译：包括形成在浅沟槽隔离（STI）焊盘上的轻掺杂多晶硅岛的低寄生电容肖特基二极管，使得多晶硅岛通过STI焊盘与下面的硅衬底完全隔离。所得到的结构减少了泄漏和电容耦合到衬底。硅化物接触结构分别连接到多晶硅岛的轻掺杂和重掺杂区域以形成肖特基结和欧姆接触，并且通过金属结构连接到形成在硅衬底上的其它组分。使用标准CMOS工艺流程形成STI焊盘，多晶硅岛和硅化物/金属触点以最小化成本。通过以反向偏置测量通过二极管的电流来提供测辐射热计检测器。这种检测器的阵列包括红外或光学图像传感器。

3. 发明授权

US07575977B2 Self-aligned LDMOS fabrication method integrated deep-sub-micron VLSI process, using a self-aligned lithography etches and implant process 有权
标题翻译：自对准LDMOS制造方法集成深亚微米VLSI工艺，使用自对准光刻蚀刻和注入工艺
公开(公告)号：US07575977B2
公开(公告)日：2009-08-18
申请号：US11691459
申请日：2007-03-26
申请人： Sharon Levin , Ira Naot , Alexei Heiman
发明人： Sharon Levin , Ira Naot , Alexei Heiman
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/26586 , H01L21/823807 , H01L21/823828 , H01L27/0922 , H01L29/0653 , H01L29/086 , H01L29/0869 , H01L29/665 , H01L29/66659 , H01L29/66689 , H01L29/7835
摘要： An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device.
摘要翻译：集成电路包括LDMOS器件和使用深亚微米VLSI制造工艺同时形成在衬底上的一个或多个低功率CMOS器件。使用双掩模蚀刻工艺对LDMOS多晶硅（多晶硅）栅极结构进行构图。第一蚀刻掩模用于限定远离深体/排出植入物的栅极结构的第一边缘。然后使用第二蚀刻掩模来限定栅极结构的第二边缘，并且随后形成深体/漏极植入物，第二蚀刻掩模然后被保持在栅极结构上。在深入植入后，形成浅的植入物和金属化以完成LDMOS器件。

4. 发明申请

US20090011576A1 Ultra-Violet Protected Tamper Resistant Embedded EEPROM 有权
标题翻译：超紫外保护防篡改嵌入式EEPROM
公开(公告)号：US20090011576A1
公开(公告)日：2009-01-08
申请号：US12207542
申请日：2008-09-10
申请人： Yakov Roizin , Yosi Netzer , Ira Naot , Myriam Buchbinder , Avi Ben-Guigui
发明人： Yakov Roizin , Yosi Netzer , Ira Naot , Myriam Buchbinder , Avi Ben-Guigui
IPC分类号： H01L21/00
CPC分类号： H01L23/552 , H01L23/585 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.
摘要翻译：单聚电解质EEPROM结构的预金属电介质结构包括UV光吸收膜，其防止EEPROM结构的浮动栅极上的电荷响应于紫外线辐射而改变。在一个实施例中，前金属介电结构包括第一预金属电介质层，位于第一预金属介电层上方的非晶硅层和位于非晶硅层之上的第二预金属介电层。

5. 发明申请

US20070223162A1 Electrostatic Discharge Protection Device For Radio Frequency Applications Based On An Isolated L-NPN Device 有权
标题翻译：基于隔离L-NPN器件的射频应用静电放电保护装置
公开(公告)号：US20070223162A1
公开(公告)日：2007-09-27
申请号：US11277607
申请日：2006-03-27
申请人： Ira Naot , Yaron Blecher
发明人： Ira Naot , Yaron Blecher
IPC分类号： H02H3/20 , H02H9/04
CPC分类号： H01L27/0259
摘要： A lateral bipolar transistor is used to protect a passive radio frequency (RF) microelectronic circuit during electrostatic discharge (ESD) events. The microelectronic circuit receives a high frequency differential input signal across first and second pads. The lateral bipolar transistor includes an n-type emitter coupled to the first pad and an n-type collector coupled to the second pad. The emitter and collector are located in a p-well, which forms the base of the transistor. The p-well is located in an isolating n-well, which in turn, is located in a p-type substrate. The n-well is coupled to receive the VDD supply voltage and the p-substrate is coupled to a VSS reference voltage. A dielectric region can be located between the emitter and collector (in the p-well).
摘要翻译：横向双极晶体管用于在静电放电（ESD）事件期间保护无源射频（RF）微电子电路。微电子电路在第一和第二焊盘上接收高频差分输入信号。横向双极晶体管包括耦合到第一焊盘的n型发射极和耦合到第二焊盘的n型集电极。发射极和集电极位于p阱中，形成晶体管的基极。 p阱位于隔离的n阱中，其又位于p型衬底中。 n阱被耦合以接收V DD电源电压，p衬底被耦合到V SS参考电压。电介质区域可以位于发射极和集电极之间（在p阱中）。

6. 发明申请

US20070166912A1 Three-dimensional control-gate architecture for single poly EPROM memory devices fabricated in planar CMOS technology 有权
标题翻译：用于平面CMOS技术制造的单个聚EPROM存储器件的三维控制门架构
公开(公告)号：US20070166912A1
公开(公告)日：2007-07-19
申请号：US11326582
申请日：2006-01-04
申请人： Amos Fenigstein , Zohar Kuritsky , Asaf Lahav , Ira Naot , Yakov Roizin
发明人： Amos Fenigstein , Zohar Kuritsky , Asaf Lahav , Ira Naot , Yakov Roizin
IPC分类号： H01L21/8244
CPC分类号： H01L27/105 , G11C16/0408 , G11C2216/10 , H01L27/11521 , H01L27/11526 , H01L27/11558 , H01L29/7833 , H01L29/94
摘要： A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.
摘要翻译：用于单多晶硅浮动栅极器件的电容器与低压和高压晶体管一起制造在半导体衬底上。每个晶体管的栅极宽度大于或等于相关联工艺的最小栅极宽度。介电层形成在衬底上，并且在电介质层上形成图案化的多晶硅结构。图案化多晶硅结构包括一个或多个窄多晶硅线，每条窄多晶硅线的宽度小于最小栅极宽度。允许使用相同导电类型的低压和高压晶体管的LDD注入进入衬底，使用图案化多晶硅结构作为掩模。热驱动周期导致在窄多晶硅线下方并入的连续扩散区域。与窄多晶硅线相邻形成的触点和连接到触点的金属-1迹线可能会增加所得到的电容。

7. 发明授权

US08379227B2 Optical metrology on textured samples 有权
标题翻译：纹理样本的光学计量学
公开(公告)号：US08379227B2
公开(公告)日：2013-02-19
申请号：US12607970
申请日：2009-10-28
申请人： Ira Naot
发明人： Ira Naot
IPC分类号： G01B11/28 , G01B11/06
CPC分类号： G01B11/02 , G01B11/06 , G01B11/0625 , G01N21/55
摘要： One or more parameters of a sample that includes a textured substrate and one or more overlying films is determined using, e.g., an optical metrology device to direct light to be incident on the sample and detecting light after the incident light interacts with the sample. The acquired data is normalized using reference data that is produced using a textured reference sample. The normalized data is then fit to simulated data that is associated with a model having an untextured substrate and one or more variable parameters. The value(s) of the one or more variable parameters from the model associated with the simulated data having the best fit is reported as measurement result.
摘要翻译：使用例如光学测量装置来确定包括纹理化衬底和一个或多个重叠膜的样品的一个或多个参数，以引导光入射到样品上并且在入射光与样品相互作用之后检测光。使用使用纹理参考样本产生的参考数据对所获取的数据进行归一化。然后将归一化数据拟合到与具有未纹理化衬底和一个或多个可变参数的模型相关联的模拟数据。来自与具有最佳拟合的模拟数据相关联的模型的一个或多个可变参数的值被报告为测量结果。

8. 发明申请

US20110096339A1 Optical Metrology On Textured Samples 有权
标题翻译：光学测量在纹理样品
公开(公告)号：US20110096339A1
公开(公告)日：2011-04-28
申请号：US12607970
申请日：2009-10-28
申请人： Ira Naot
发明人： Ira Naot
IPC分类号： G01B11/02 , G01N21/55 , G06F17/00
CPC分类号： G01B11/02 , G01B11/06 , G01B11/0625 , G01N21/55
摘要： One or more parameters of a sample that includes a textured substrate and one or more overlying films is determined using, e.g., an optical metrology device to direct light to be incident on the sample and detecting light after the incident light interacts with the sample. The acquired data is normalized using reference data that is produced using a textured reference sample. The normalized data is then fit to simulated data that is associated with a model having an untextured substrate and one or more variable parameters. The value(s) of the one or more variable parameters from the model associated with the simulated data having the best fit is reported as measurement result.
摘要翻译：使用例如光学测量装置来确定包括纹理化衬底和一个或多个重叠膜的样品的一个或多个参数，以引导光入射到样品上并且在入射光与样品相互作用之后检测光。使用使用纹理参考样本产生的参考数据对所获取的数据进行归一化。然后将归一化数据拟合到与具有未纹理化衬底和一个或多个可变参数的模型相关联的模拟数据。来自与具有最佳拟合的模拟数据相关联的模型的一个或多个可变参数的值被报告为测量结果。

9. 发明授权

US07795087B2 Ultra-violet protected tamper resistant embedded EEPROM 有权
标题翻译：紫外线防篡改嵌入式EEPROM
公开(公告)号：US07795087B2
公开(公告)日：2010-09-14
申请号：US12207542
申请日：2008-09-10
申请人： Yakov Roizin , Yossi Netzer , Ira Naot , Myriam Buchbinder , Avi Ben-Guigui
发明人： Yakov Roizin , Yossi Netzer , Ira Naot , Myriam Buchbinder , Avi Ben-Guigui
IPC分类号： H01L21/8239
CPC分类号： H01L23/552 , H01L23/585 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.
摘要翻译：单聚电解质EEPROM结构的预金属电介质结构包括UV光吸收膜，其防止EEPROM结构的浮动栅极上的电荷响应于紫外线辐射而改变。在一个实施例中，前金属介电结构包括第一预金属电介质层，位于第一预金属介电层上方的非晶硅层和位于非晶硅层之上的第二预金属介电层。

10. 发明授权

US07754564B2 Method for fabricating three-dimensional control-gate architecture for single poly EPROM memory devices in planar CMOS technology 有权
标题翻译：用于在平面CMOS技术中制造单个多EPROM存储器件的三维控制栅结构的方法
公开(公告)号：US07754564B2
公开(公告)日：2010-07-13
申请号：US12046913
申请日：2008-03-12
申请人： Amos Fenigstein , Zohar Kuritsky , Assaf Lahav , Ira Naot , Yakov Roizin
发明人： Amos Fenigstein , Zohar Kuritsky , Assaf Lahav , Ira Naot , Yakov Roizin
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , G11C16/0408 , G11C2216/10 , H01L27/11521 , H01L27/11526 , H01L27/11558 , H01L29/7833 , H01L29/94
摘要： A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.
摘要翻译：用于单多晶硅浮动栅极器件的电容器与低压和高压晶体管一起制造在半导体衬底上。每个晶体管的栅极宽度大于或等于相关联工艺的最小栅极宽度。介电层形成在衬底上，并且在电介质层上形成图案化的多晶硅结构。图案化多晶硅结构包括一个或多个窄多晶硅线，每条窄多晶硅线的宽度小于最小栅极宽度。允许使用相同导电类型的低压和高压晶体管的LDD注入进入衬底，使用图案化多晶硅结构作为掩模。热驱动周期导致在窄多晶硅线下方并入的连续扩散区域。与窄多晶硅线相邻形成的触点和连接到触点的金属-1迹线可能增加所得到的电容。

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