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1. 发明授权

US08507996B2 Block contact plugs for MOS devices 有权
标题翻译：块接触器用于MOS器件
公开(公告)号：US08507996B2
公开(公告)日：2013-08-13
申请号：US12789046
申请日：2010-05-27
申请人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
发明人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
IPC分类号： H01L23/528
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.
摘要翻译：集成电路结构包括半导体衬底; 覆盖半导体衬底的栅极堆叠; 在栅极堆叠的侧壁上的栅极间隔物; 具有接触所述栅极隔离物的侧壁的内边缘的第一接触插塞和具有所述栅极堆叠的顶表面的顶表面水平; 以及第二接触插头，并且与第一接触插塞接触。第二接触插塞的横截面积小于第一接触插塞的横截面面积。

2. 发明申请

US20110068411A1 Block Contact Plugs for MOS Devices 有权
标题翻译： MOS器件的块式触点插头
公开(公告)号：US20110068411A1
公开(公告)日：2011-03-24
申请号：US12789046
申请日：2010-05-27
申请人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
发明人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
IPC分类号： H01L29/78
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.
摘要翻译：集成电路结构包括半导体衬底; 覆盖半导体衬底的栅极堆叠; 在栅极堆叠的侧壁上的栅极间隔物; 具有接触所述栅极隔离物的侧壁的内边缘的第一接触插塞和具有所述栅极堆叠的顶表面的顶表面水平; 以及第二接触插头，并且与第一接触插塞接触。第二接触插塞的横截面积小于第一接触插塞的横截面面积。

3. 发明授权

US08946828B2 Semiconductor device having elevated structure and method of manufacturing the same 有权
标题翻译：具有升高的结构的半导体器件及其制造方法
公开(公告)号：US08946828B2
公开(公告)日：2015-02-03
申请号：US12702683
申请日：2010-02-09
申请人： Sey-Ping Sun , Tsung-Lin Lee , Chin-Hsiang Lin , Chih-Hao Chang , Chen-Nan Yeh , Chao-An Jong
发明人： Sey-Ping Sun , Tsung-Lin Lee , Chin-Hsiang Lin , Chih-Hao Chang , Chen-Nan Yeh , Chao-An Jong
IPC分类号： H01L29/78 , H01L21/768 , H01L29/66
CPC分类号： H01L29/4232 , H01L21/76834 , H01L21/76849 , H01L21/76897 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.
摘要翻译：半导体器件包括半导体衬底; 覆盖衬底的栅极堆叠，形成在栅极堆叠的侧壁上的间隔物，以及覆盖栅极堆叠的保护层，用于填充由间隔物和栅极堆叠的顶表面围绕的空间的至少一部分。间隔件的顶表面高于栅极堆叠的顶表面。

4. 发明申请

US20110193144A1 SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有高度结构的半导体器件及其制造方法
公开(公告)号：US20110193144A1
公开(公告)日：2011-08-11
申请号：US12702683
申请日：2010-02-09
申请人： Sey-Ping Sun , Tsung-Lin Lee , Chin-Hsiang Lin , Chih-Hao Chang , Chen-Nan Yeh , Chao-An Jong
发明人： Sey-Ping Sun , Tsung-Lin Lee , Chin-Hsiang Lin , Chih-Hao Chang , Chen-Nan Yeh , Chao-An Jong
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/4232 , H01L21/76834 , H01L21/76849 , H01L21/76897 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.
摘要翻译：半导体器件包括半导体衬底; 覆盖衬底的栅极堆叠，形成在栅极堆叠的侧壁上的间隔物，以及覆盖栅极堆叠的保护层，用于填充由间隔物和栅极堆叠的顶表面围绕的空间的至少一部分。间隔件的顶表面高于栅极堆叠的顶表面。

5. 发明授权

US08497528B2 Method for fabricating a strained structure 有权
标题翻译：制造应变结构的方法
公开(公告)号：US08497528B2
公开(公告)日：2013-07-30
申请号：US12775006
申请日：2010-05-06
申请人： Tsung-Lin Lee , Chih-Hao Chang , Chih-Hsin Ko , Feng Yuan , Jeff J. Xu
发明人： Tsung-Lin Lee , Chih-Hao Chang , Chih-Hsin Ko , Feng Yuan , Jeff J. Xu
IPC分类号： H01L29/66
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/30604 , H01L21/31 , H01L21/31116 , H01L21/76 , H01L29/0653 , H01L29/0847 , H01L29/0856 , H01L29/0873 , H01L29/1608 , H01L29/165 , H01L29/6653 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.
摘要翻译：一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。该凹腔具有下部和上部。下部具有第一应变层和第一介电膜。第一应变层设置在隔离结构和第一介电膜之间。第一电介质膜的厚度小于第一应变层的厚度。上部具有覆盖在第一应变层和第一介电膜上的第二应变层。

6. 发明授权

US09171929B2 Strained structure of semiconductor device and method of making the strained structure 有权
标题翻译：半导体器件的应变结构和制造应变结构的方法
公开(公告)号：US09171929B2
公开(公告)日：2015-10-27
申请号：US13487860
申请日：2012-06-04
申请人： Tsung-Lin Lee , Chih Chieh Yeh , Feng Yuan , Cheng-Yi Peng , Clement Hsingjen Wann
发明人： Tsung-Lin Lee , Chih Chieh Yeh , Feng Yuan , Cheng-Yi Peng , Clement Hsingjen Wann
IPC分类号： H01L29/78 , H01L27/092 , H01L29/66 , H01L29/10 , H01L29/165 , H01L21/8238 , H01L21/02
CPC分类号： H01L29/66636 , H01L21/02529 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/1054 , H01L29/165 , H01L29/66651 , H01L29/7848
摘要： An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.
摘要翻译：用于场效应晶体管（FET）的示例性结构包括：硅衬底，其包括第一表面; 在所述第一表面上的通道部分，其中所述通道部分具有在所述第一表面上方的第一高度处的第二表面和平行于第一表面的长度; 以及沿沟道部分的长度围绕沟道部分的两个源极/漏极（S / D）区域，其中两个S / D区域包括SiGe，Ge，Si，SiC，GeSn，SiGeSn，SiSn，或III-V材料。

7. 发明申请

US20130228862A1 SEMICONDUCTOR DEVICE HAVING A STRAINED REGION 有权
标题翻译：具有应变区域的半导体器件
公开(公告)号：US20130228862A1
公开(公告)日：2013-09-05
申请号：US13411214
申请日：2012-03-02
申请人： Tsung-Lin Lee , Feng Yuan , Hung-Li Chiang , Chih Chieh Yeh
发明人： Tsung-Lin Lee , Feng Yuan , Hung-Li Chiang , Chih Chieh Yeh
IPC分类号： H01L27/12 , H01L21/336 , H01L21/20
CPC分类号： H01L29/66803 , H01L21/26513 , H01L21/26586 , H01L21/30604 , H01L21/823418 , H01L21/823431 , H01L21/823807 , H01L21/823814 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.
摘要翻译：本公开提供了提供应变外延区域的装置和方法。提供一种半导体制造方法，其包括在半导体衬底的翅片上形成栅极结构，并在与栅极结构相邻的鳍中形成凹陷。然后改变凹槽的侧壁。示例性改变包括具有改变的轮廓，处理侧壁以及在侧壁上形成层。然后在凹槽中生长外延区域。外延区域与凹陷的改变的侧壁接触并且是应变的外延区域。

8. 发明授权

US08373238B2 FinFETs with multiple Fin heights 有权
标题翻译： FinFET具有多个鳍高度
公开(公告)号：US08373238B2
公开(公告)日：2013-02-12
申请号：US12843595
申请日：2010-07-26
申请人： Tsung-Lin Lee , Chih Chieh Yeh , Chang-Yun Chang , Feng Yuan
发明人： Tsung-Lin Lee , Chih Chieh Yeh , Chang-Yun Chang , Feng Yuan
IPC分类号： H01L27/088
CPC分类号： H01L29/66666 , H01L21/76 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/785
摘要： An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.
摘要翻译：集成电路结构包括半导体衬底和半导体衬底上的FinFET。 FinFET包括半导体鳍片; 顶表面上的栅极电介质和半导体鳍片的侧壁; 栅电极上的栅电极; 以及在半导体鳍片的端部处的源极/漏极区域。第一对浅沟槽隔离（STI）区域包括直接在源极/漏极区域的下方部分的部分，其中第一对STI区域被分隔开并邻接半导体条带。第一对STI区域还具有第一顶面。第二对STI区域包括直接位于栅极电极下方的部分，其中第二对STI区域彼此分离并邻接半导体条带。第二对STI区域具有高于第一顶表面的第二顶表面。

9. 发明申请

US20110121406A1 FinFETs with Different Fin Heights 有权
标题翻译：具有不同翅片高度的FinFET
公开(公告)号：US20110121406A1
公开(公告)日：2011-05-26
申请号：US12871655
申请日：2010-08-30
申请人： Tsung-Lin Lee , Chih Cheih Yeh , Chang-Yun Chang , Feng Yuan
发明人： Tsung-Lin Lee , Chih Cheih Yeh , Chang-Yun Chang , Feng Yuan
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L21/823431 , H01L21/266 , H01L21/76224 , H01L21/823437 , H01L21/823481 , H01L27/0886 , H01L27/1104 , H01L27/1116 , H01L29/0649 , H01L29/41791 , H01L29/66795 , H01L29/785
摘要： An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
摘要翻译：集成电路结构包括包括第一器件区域中的第一部分和第二器件区域中的第二部分的半导体衬底。第一半导体鳍片在半导体衬底之上并且具有第一鳍片高度。第二半导体鳍片在半导体衬底之上并且具有第二鳍片高度。第一鳍高度大于第二翅片高度。

10. 发明申请

US20110115024A1 Non-Uniform Semiconductor Device Active Area Pattern Formation 有权
标题翻译：非均匀半导体器件有源区域图形形成
公开(公告)号：US20110115024A1
公开(公告)日：2011-05-19
申请号：US12856343
申请日：2010-08-13
申请人： Tsung-Lin Lee , Shao-Ming Yu
发明人： Tsung-Lin Lee , Shao-Ming Yu
IPC分类号： H01L27/088 , H01L21/302 , H01L21/28
CPC分类号： H01L27/0207 , H01L21/823431 , H01L27/088 , H01L27/0886
摘要： In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of the respective active area. The edges of the at least three active areas form an arc.
摘要翻译：根据实施例，半导体器件包括至少三个有效区域。至少三个活动区域是接近的。所述至少三个有效区域的纵轴是平行的，并且所述至少三个有效区域中的每一个包括与相应有效区域的纵向轴线相交的边缘。至少三个活动区域的边缘形成弧。

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