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1. 发明授权

US06952965B2 Vertical MEMS gyroscope by horizontal driving 有权
标题翻译：垂直MEMS陀螺仪通过水平驱动
公开(公告)号：US06952965B2
公开(公告)日：2005-10-11
申请号：US10744099
申请日：2003-12-24
申请人： Seok-jin Kang , Seok-whan Chung , Moon-chul Lee , Kyu-dong Jung , Seog-soo Hong
发明人： Seok-jin Kang , Seok-whan Chung , Moon-chul Lee , Kyu-dong Jung , Seog-soo Hong
IPC分类号： B81B7/00 , B81B3/00 , B81B5/00 , B81C1/00 , G01C19/56 , G01C19/5762 , G01C19/5769 , G01P9/04
CPC分类号： G01C19/5762 , B81B3/0059 , B81B2201/0242 , B81B2203/051 , B81B2203/053
摘要： A vertical MEMS gyroscope by horizontal driving includes a substrate, a support layer fixed on an upper surface of an area of the substrate, a driving structure floating above the substrate and having a portion fixed to an upper surface of the support layer and another portion in parallel with the fixed portion, the driving structure having a predetermined area capable of vibrating in a predetermined direction parallel to the substrate, a detecting structure fixed to the driving structure on a same plane as the driving structure, and having a predetermined area capable of vibrating in a vertical direction with respect to the substrate, a cap wafer bonded with the substrate positioned above the driving structure and the detecting structure, and a fixed vertical displacement detection electrode formed at a predetermined location of an underside of the cap wafer, for detecting displacement of the detecting structure in the vertical direction.
摘要翻译：通过水平驱动的垂直MEMS陀螺仪包括基板，固定在基板的区域的上表面上的支撑层，浮动在基板上方并具有固定到支撑层的上表面的部分的驱动结构，平行于固定部分，驱动结构具有能够在与基板平行的预定方向上振动的预定区域;检测结构，其在与驱动结构相同的平面上固定到驱动结构，并且具有能够振动的预定区域在相对于基板的垂直方向上，与位于驱动结构上方的基板接合的盖晶片和检测结构，以及形成在盖晶片的下侧的预定位置处的固定垂直位移检测电极，用于检测位移的检测结构。

2. 发明授权

US07172916B2 Method and apparatus for vacuum-mounting a micro electro mechanical system on a substrate 失效
标题翻译：将微机电系统真空安装在基板上的方法和装置
公开(公告)号：US07172916B2
公开(公告)日：2007-02-06
申请号：US10701552
申请日：2003-11-06
申请人： Kyu-dong Jung , Chan-Bong Jun , Hyung Choi , Seok-jin Kang , Seog-woo Hong , Seok-whan Chung , Moon-chul Lee , Eun-sung Lee
发明人： Kyu-dong Jung , Chan-Bong Jun , Hyung Choi , Seok-jin Kang , Seog-woo Hong , Seok-whan Chung , Moon-chul Lee , Eun-sung Lee
IPC分类号： H01L21/00
CPC分类号： B81C1/00285
摘要： A method and apparatus for vacuum-mounting at least one micro electro mechanical system (MEMS) on a substrate includes a gas injecting section for injecting an inert gas into a vacuum chamber; a substrate aligning section for aligning a semiconductor substrate and a cover, the cover having a cavity formed therein and a getter attached to an interior surface of the cavity; a bonding section for bonding the semiconductor substrate and the cover together; and a controlling section for controlling the substrate aligning section to align the semiconductor and the cover, for controlling the gas injecting section to inject the inert gas into the vacuum chamber, and for controlling the bonding section to bond the semiconductor substrate and the cover together after the inert gas is injected.
摘要翻译：用于真空安装至少一个微机电系统（MEMS）在基板上的方法和装置包括用于将惰性气体注入真空室的气体注入部分; 用于对准半导体衬底和盖的衬底对准部分，所述盖具有形成在其中的空腔和附着到腔的内表面的吸气剂; 用于将半导体衬底和盖结合在一起的接合部分; 以及控制部分，用于控制衬底对准部分以对准半导体和盖子，用于控制气体注入部分以将惰性气体注入真空室中，并且用于控制接合部分将半导体衬底和盖子结合在一起，之后注入惰性气体。

3. 发明授权

US06835594B2 Metal wiring method for an undercut 有权
公开(公告)号：US06835594B2
公开(公告)日：2004-12-28
申请号：US10686769
申请日：2003-10-17
申请人： Ci-moo Shong , Seok-jin Kang , Seok-whan Chung , Moon-chul Lee , Kyu-dong Jung , Jong-seok Kim , Chan-bong Jun , Seog-woo Hong , Jung-ho Kang
发明人： Ci-moo Shong , Seok-jin Kang , Seok-whan Chung , Moon-chul Lee , Kyu-dong Jung , Jong-seok Kim , Chan-bong Jun , Seog-woo Hong , Jung-ho Kang
IPC分类号： H01L2144
CPC分类号： B81B7/0006 , H01L21/76877 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A metal wiring method for an undercut in a MEMS packaging process includes disposing a MEMS element on a silicon substrate, welding a glass wafer to an upper portion of the silicon substrate having the MEMS element disposed thereon, the glass wafer having a hole formed therein for connecting a metal wiring, depositing a thin metal film for the metal wiring in the hole, and ion-mealing the deposited thin metal film. By the ion-mealing, the method is capable of connecting a metal wiring to a via hole having an undercut.

4. 发明授权

US07084073B2 Method of forming a via hole through a glass wafer 有权
标题翻译：通过玻璃晶片形成通孔的方法
公开(公告)号：US07084073B2
公开(公告)日：2006-08-01
申请号：US10681217
申请日：2003-10-09
申请人： Moon-chul Lee , Hyung Choi , Kyu-dong Jung , Mi Jang , Seog-woo Hong , Seok-whan Chung , Chan-bong Jun , Seok-jin Kang
发明人： Moon-chul Lee , Hyung Choi , Kyu-dong Jung , Mi Jang , Seog-woo Hong , Seok-whan Chung , Chan-bong Jun , Seok-jin Kang
IPC分类号： H01L21/302
CPC分类号： B81C1/00087 , H01L21/486 , H01L23/13 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a via hole through a glass wafer includes depositing a material layer on an outer surface of the glass wafer, the material layer having a selection ratio higher than that of the glass wafer, forming a via-patterned portion on one side of the material layer, performing a first etching in which the via-patterned portion is etched to form a preliminary via hole, eliminating any remaining patterning material used in the formation of the via-patterned portion, performing a second etching in which the preliminary via hole is etched to form a via hole having a smooth surface and extending through the glass wafer, and eliminating the material layer. The method according to the present invention is able to form a via hole through a glass wafer without allowing formation of an undercut or minute cracks, thereby increasing the yield and reliability of MEMS elements.
摘要翻译：通过玻璃晶片形成通孔的方法包括在玻璃晶片的外表面上沉积材料层，该材料层的选择比率高于玻璃晶片的选择比，在玻璃晶片的一侧上形成通孔图案部分所述材料层进行蚀刻所述通路图案部分以形成预备通孔的第一蚀刻，消除在形成所述通路图案部分中使用的剩余图案材料，进行第二蚀刻，其中所述预通孔被蚀刻以形成具有光滑表面并延伸穿过玻璃晶片的通孔，并且消除材料层。根据本发明的方法能够通过玻璃晶片形成通孔，而不会形成底切或微小的裂缝，从而提高MEMS元件的成品率和可靠性。

5. 发明申请

US20060083904A1 Wiring apparatus, protecting cap for device package using the same, and a method for manufacturing them 审中-公开
标题翻译：接线装置，使用其的器件封装的保护帽及其制造方法
公开(公告)号：US20060083904A1
公开(公告)日：2006-04-20
申请号：US11252588
申请日：2005-10-19
申请人： Seok-whan Chung , Moon-chul Lee , Woon-bae Kim
发明人： Seok-whan Chung , Moon-chul Lee , Woon-bae Kim
IPC分类号： B32B3/00 , B32B18/00
CPC分类号： H05K1/115 , H01L23/04 , H01L23/49827 , H01L2924/0002 , H05K1/0306 , H05K2201/0179 , H05K2201/068 , H05K2201/09563 , H05K2201/09581 , Y10T428/24917 , Y10T428/24926 , H01L2924/00
摘要： A wiring apparatus including a substrate, a via-hole penetrating the substrate, a buffer layer formed on an inner surface of the via-hole, and a plating layer filling filing the via hole inside of the buffer layer. When the wiring apparatus is applied to a protecting cap for device package, a difference in thermal expansion coefficient generated between the substrate and the plating layer can be compensated, thereby preventing damage to the packaging substrate even upon application of thermal impact. Methods for fabricating the wiring apparatus and a protecting cap for a device package using the above wiring processes are also disclosed.
摘要翻译：包括基板，穿透基板的通孔，形成在通孔的内表面上的缓冲层的布线装置以及填充缓冲层内的通孔的镀层。当将布线装置应用于装置封装的保护帽时，可以补偿在基板和镀层之间产生的热膨胀系数的差异，从而即使在施加热冲击时也防止对包装基板的损坏。还公开了使用上述布线方法制造布线装置的方法和用于装置封装的保护帽。

6. 发明申请

US20060273444A1 Packaging chip and packaging method thereof 失效
标题翻译：包装芯片及其包装方法
公开(公告)号：US20060273444A1
公开(公告)日：2006-12-07
申请号：US11390220
申请日：2006-03-28
申请人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
发明人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
IPC分类号： H01L23/48
CPC分类号： H01L23/055 , H01L23/04 , H01L27/14618 , H01L2224/16
摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.
摘要翻译：提供电路模块封装的封装芯片和封装电路模块的方法。包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔，将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

7. 发明申请

US20060255443A1 Multi stack packaging chip and method of manufacturing the same 有权
标题翻译：多堆叠封装芯片及其制造方法相同
公开(公告)号：US20060255443A1
公开(公告)日：2006-11-16
申请号：US11391211
申请日：2006-03-29
申请人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , Moon-chul Lee , Kyu-dong Jung
发明人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , Moon-chul Lee , Kyu-dong Jung
IPC分类号： H01L23/02
CPC分类号： B81C1/0023 , B81B7/007 , B81C2203/0118 , H01L23/04 , H01L23/49816 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2224/48463 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/16235 , H01L2924/19041 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.
摘要翻译：提供了一种多层封装芯片及其制造方法。该方法包括在第一晶片上形成至少一个第二电路元件; 形成具有空腔的第二晶片和与所述腔相对形成的一个第三电路元件; 在第二晶片上形成焊料; 以及将所述第二晶片与所述第一晶片组合以使得所述第二电路元件和所述空腔对应。芯片包括倒装芯片封装芯片，其中使用第一晶片封装第一电路元件; 形成在第一晶片上的第二电路元件; 第二晶片，其具有空腔并与所述第一晶片组合，使得所述空腔和所述第二电路元件对应; 形成在第二晶片上的第三电路元件; 以及形成在所述第二晶片上的焊料，所述焊料将所述第二晶片电耦合到封装衬底。

8. 发明授权

US07579685B2 Wafer level packaging cap and fabrication method thereof 有权
标题翻译：晶圆级封装盖及其制造方法
公开(公告)号：US07579685B2
公开(公告)日：2009-08-25
申请号：US11339500
申请日：2006-01-26
申请人： Moon-chul Lee , Woon-bae Kim , Kae-dong Back , Qian Wang , Jun-sik Hwang , Kyu-dong Jung
发明人： Moon-chul Lee , Woon-bae Kim , Kae-dong Back , Qian Wang , Jun-sik Hwang , Kyu-dong Jung
IPC分类号： H01L23/12 , H01L23/043
CPC分类号： B81C1/00301 , B81B2207/095 , H01L21/76898 , H01L23/04 , H01L23/10 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.
摘要翻译：提供了一种用于晶片级封装的晶片级封装盖及其方法。覆盖其上具有器件的器件晶片的晶片级封装盖包括盖晶片，其在底表面上具有提供用于接收器件的空间并与器件晶片整体结合的空腔，形成在底部的多个金属线盖片晶片的表面对应于形成在器件晶片上以电连接到器件的多个器件焊盘，多个缓冲部分连接到多个金属线并且包括具有多个沟槽的缓冲晶片和填充在所述多个槽中的金属，多个连接杆，电连接到所述多个缓冲部分，并且从所述缓冲部分的顶部穿透所述盖片;以及形成在所述盖片的顶表面上的多个帽垫并且电连接到多个连接杆。

9. 发明授权

US07432781B2 Monolithic duplexer and fabrication method thereof 有权
标题翻译：单片双工器及其制造方法
公开(公告)号：US07432781B2
公开(公告)日：2008-10-07
申请号：US11392624
申请日：2006-03-30
申请人： Sang-chul Sul , Duck-hwan Kim , Chul-soo Kim , In-sang Song , Moon-chul Lee , Kyu-dong Jung , Jea-shik Shin
发明人： Sang-chul Sul , Duck-hwan Kim , Chul-soo Kim , In-sang Song , Moon-chul Lee , Kyu-dong Jung , Jea-shik Shin
IPC分类号： H03H7/46
CPC分类号： H03H3/02 , H03H9/0571 , H03H9/706
摘要： A monolithic duplexer and a fabrication method thereof. The monolithic duplexer includes a device wafer, a plurality of elements distanced from each other on a top portion of a device wafer, first sealing parts formed on the top portion of the device wafer, and a plurality of first ground planes formed between the plurality of elements. A cap wafer is also provided having an etched area for packaging the device wafer, a plurality of protrusion parts, a plurality of ground posts, and cavities. Second sealing parts are formed on a bottom portion of the protrusion parts, and a plurality of second ground planes cover the plurality of ground posts. Via holes vertically penetrate the cap wafer to connect to the plurality of the second ground planes, and ground terminals are formed on top portions of the via holes. The first sealing parts and the first ground planes are attached to the second sealing parts and the second ground planes, respectively.
摘要翻译：一种单片双工器及其制造方法。单片双工器包括器件晶片，在器件晶片的顶部彼此远离的多个元件，形成在器件晶片的顶部上的第一密封部分和形成在器件晶片的顶部之间的多个第一接地平面元素。还提供了盖晶片，其具有用于封装器件晶片，多个突出部分，多个接地柱和空腔的蚀刻区域。第二密封部分形成在突出部分的底部上，并且多个第二接地平面覆盖多个接地柱。通孔垂直穿过盖晶片以连接到多个第二接地平面，并且接地端子形成在通孔的顶部上。第一密封部分和第一接地平面分别附接到第二密封部分和第二接地平面。

10. 发明授权

US07408257B2 Packaging chip and packaging method thereof 失效
标题翻译：包装芯片及其包装方法
公开(公告)号：US07408257B2
公开(公告)日：2008-08-05
申请号：US11390220
申请日：2006-03-28
申请人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
发明人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
IPC分类号： H01L23/04
CPC分类号： H01L23/055 , H01L23/04 , H01L27/14618 , H01L2224/16
摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.
摘要翻译：提供电路模块封装的封装芯片和封装电路模块的方法。包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔，将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

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