专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07579685B2 Wafer level packaging cap and fabrication method thereof 有权
标题翻译：晶圆级封装盖及其制造方法
公开(公告)号：US07579685B2
公开(公告)日：2009-08-25
申请号：US11339500
申请日：2006-01-26
申请人： Moon-chul Lee , Woon-bae Kim , Kae-dong Back , Qian Wang , Jun-sik Hwang , Kyu-dong Jung
发明人： Moon-chul Lee , Woon-bae Kim , Kae-dong Back , Qian Wang , Jun-sik Hwang , Kyu-dong Jung
IPC分类号： H01L23/12 , H01L23/043
CPC分类号： B81C1/00301 , B81B2207/095 , H01L21/76898 , H01L23/04 , H01L23/10 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.
摘要翻译：提供了一种用于晶片级封装的晶片级封装盖及其方法。覆盖其上具有器件的器件晶片的晶片级封装盖包括盖晶片，其在底表面上具有提供用于接收器件的空间并与器件晶片整体结合的空腔，形成在底部的多个金属线盖片晶片的表面对应于形成在器件晶片上以电连接到器件的多个器件焊盘，多个缓冲部分连接到多个金属线并且包括具有多个沟槽的缓冲晶片和填充在所述多个槽中的金属，多个连接杆，电连接到所述多个缓冲部分，并且从所述缓冲部分的顶部穿透所述盖片;以及形成在所述盖片的顶表面上的多个帽垫并且电连接到多个连接杆。

2. 发明申请

US20060175707A1 Wafer level packaging cap and fabrication method thereof 有权
公开(公告)号：US20060175707A1
公开(公告)日：2006-08-10
申请号：US11339500
申请日：2006-01-26
申请人： Moon-chul Lee , Woon-bae Kim , Kae-dong Back , Qian Wang , Jun-sik Hwang , Kyu-dong Jung
发明人： Moon-chul Lee , Woon-bae Kim , Kae-dong Back , Qian Wang , Jun-sik Hwang , Kyu-dong Jung
IPC分类号： H01L23/52
CPC分类号： B81C1/00301 , B81B2207/095 , H01L21/76898 , H01L23/04 , H01L23/10 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.

3. 发明申请

US20060273444A1 Packaging chip and packaging method thereof 失效
标题翻译：包装芯片及其包装方法
公开(公告)号：US20060273444A1
公开(公告)日：2006-12-07
申请号：US11390220
申请日：2006-03-28
申请人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
发明人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
IPC分类号： H01L23/48
CPC分类号： H01L23/055 , H01L23/04 , H01L27/14618 , H01L2224/16
摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.
摘要翻译：提供电路模块封装的封装芯片和封装电路模块的方法。包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔，将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

4. 发明授权

US07408257B2 Packaging chip and packaging method thereof 失效
标题翻译：包装芯片及其包装方法
公开(公告)号：US07408257B2
公开(公告)日：2008-08-05
申请号：US11390220
申请日：2006-03-28
申请人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
发明人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
IPC分类号： H01L23/04
CPC分类号： H01L23/055 , H01L23/04 , H01L27/14618 , H01L2224/16
摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.
摘要翻译：提供电路模块封装的封装芯片和封装电路模块的方法。包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔，将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

5. 发明授权

US07335974B2 Multi stack packaging chip and method of manufacturing the same 有权
标题翻译：多堆叠封装芯片及其制造方法相同
公开(公告)号：US07335974B2
公开(公告)日：2008-02-26
申请号：US11391211
申请日：2006-03-29
申请人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , Moon-chul Lee , Kyu-dong Jung
发明人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , Moon-chul Lee , Kyu-dong Jung
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： B81C1/0023 , B81B7/007 , B81C2203/0118 , H01L23/04 , H01L23/49816 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2224/48463 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/16235 , H01L2924/19041 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.
摘要翻译：提供了一种多层封装芯片及其制造方法。该方法包括在第一晶片上形成至少一个第二电路元件; 形成具有空腔的第二晶片和与所述腔相对形成的一个第三电路元件; 在第二晶片上形成焊料; 以及将所述第二晶片与所述第一晶片组合以使得所述第二电路元件和所述空腔对应。芯片包括倒装芯片封装芯片，其中使用第一晶片封装第一电路元件; 形成在第一晶片上的第二电路元件; 第二晶片，其具有空腔并与所述第一晶片组合，使得所述空腔和所述第二电路元件对应; 形成在第二晶片上的第三电路元件; 以及形成在所述第二晶片上的焊料，所述焊料将所述第二晶片电耦合到封装衬底。

6. 发明申请

US20060255443A1 Multi stack packaging chip and method of manufacturing the same 有权
标题翻译：多堆叠封装芯片及其制造方法相同
公开(公告)号：US20060255443A1
公开(公告)日：2006-11-16
申请号：US11391211
申请日：2006-03-29
申请人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , Moon-chul Lee , Kyu-dong Jung
发明人： Jun-sik Hwang , Woon-bae Kim , Chang-youl Moon , Moon-chul Lee , Kyu-dong Jung
IPC分类号： H01L23/02
CPC分类号： B81C1/0023 , B81B7/007 , B81C2203/0118 , H01L23/04 , H01L23/49816 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2224/48463 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/16235 , H01L2924/19041 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.
摘要翻译：提供了一种多层封装芯片及其制造方法。该方法包括在第一晶片上形成至少一个第二电路元件; 形成具有空腔的第二晶片和与所述腔相对形成的一个第三电路元件; 在第二晶片上形成焊料; 以及将所述第二晶片与所述第一晶片组合以使得所述第二电路元件和所述空腔对应。芯片包括倒装芯片封装芯片，其中使用第一晶片封装第一电路元件; 形成在第一晶片上的第二电路元件; 第二晶片，其具有空腔并与所述第一晶片组合，使得所述空腔和所述第二电路元件对应; 形成在第二晶片上的第三电路元件; 以及形成在所述第二晶片上的焊料，所述焊料将所述第二晶片电耦合到封装衬底。

7. 发明申请

US20070013058A1 Packaging chip having interconnection electrodes directly connected to plural wafers and fabrication method therefor 有权
标题翻译：具有直接连接到多个晶片的互连电极的封装芯片及其制造方法
公开(公告)号：US20070013058A1
公开(公告)日：2007-01-18
申请号：US11481012
申请日：2006-07-06
申请人： Min-seog Choi , Kae-dong Back , In-sang Song , Woon-bae Kim , Byung-gil Jeong , Kyu-dong Jung
发明人： Min-seog Choi , Kae-dong Back , In-sang Song , Woon-bae Kim , Byung-gil Jeong , Kyu-dong Jung
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H03H9/0547
摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.
摘要翻译：形成有多个晶片的封装芯片。封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。多个晶片中的至少一个或多个在其上安装预定的电路装置。此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。

8. 发明授权

US07786573B2 Packaging chip having interconnection electrodes directly connected to plural wafers 有权
标题翻译：具有直接连接到多个晶片的互连电极的封装芯片
公开(公告)号：US07786573B2
公开(公告)日：2010-08-31
申请号：US11481012
申请日：2006-07-06
申请人： Min-seog Choi , Kae-dong Back , In-sang Song , Woon-bae Kim , Byung-gil Jeong , Kyu-dong Jung
发明人： Min-seog Choi , Kae-dong Back , In-sang Song , Woon-bae Kim , Byung-gil Jeong , Kyu-dong Jung
IPC分类号： H01L23/34 , H01R12/16 , H05K1/11
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H03H9/0547
摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.
摘要翻译：形成有多个晶片的封装芯片。封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。多个晶片中的至少一个或多个在其上安装预定的电路装置。此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。

9. 发明授权

US07545017B2 Wafer level package for surface acoustic wave device and fabrication method thereof 有权
标题翻译：用于表面声波器件的晶片级封装及其制造方法
公开(公告)号：US07545017B2
公开(公告)日：2009-06-09
申请号：US11447969
申请日：2006-06-07
申请人： Moon-chul Lee , Jun-sik Hwang , Ji-hyuk Lim , Woon-bae Kim
发明人： Moon-chul Lee , Jun-sik Hwang , Ji-hyuk Lim , Woon-bae Kim
IPC分类号： H01L29/84
CPC分类号： H03H9/1092 , H01L2224/48091 , H01L2224/48227 , H01L2924/16195 , H01L2924/00014
摘要： A wafer level package for a surface acoustic wave (SAW) device and a fabrication method thereof. The SAW device wafer level package includes a SAW device in which a SAW element is formed on a top surface of a device wafer, a cap wafer which is bonded with a top surface of the SAW device and has a viahole penetrating the cap wafer, and a conductive member to fill a part of the viahole. The viahole has a first via portion and a second via portion, the first via portion has a gradually smaller diameter from a bottom surface of the cap wafer until a certain depth, and the second via portion has a gradually greater diameter from the first via portion until a top surface of the cap wafer.
摘要翻译：一种用于表面声波（SAW）器件的晶片级封装及其制造方法。 SAW器件晶片级封装包括SAW器件，其中SAW元件形成在器件晶片的顶表面上，盖晶片与SAW器件的顶表面结合并具有穿透盖晶片的通孔，以及用于填充通孔的一部分的导电构件。通孔具有第一通孔部分和第二通孔部分，第一通孔部分具有从盖子晶片的底表面到一定深度的逐渐变小的直径，并且第二通孔部分具有从第一通孔部分直到盖晶片的顶表面。

10. 发明授权

US07408434B2 Inductor embedded in substrate, manufacturing method thereof, micro device package, and manufacturing method of cap for micro device package 有权
标题翻译：嵌入基板的电感器，其制造方法，微器件封装以及用于微器件封装的帽的制造方法
公开(公告)号：US07408434B2
公开(公告)日：2008-08-05
申请号：US11400637
申请日：2006-04-10
申请人： Moon-chul Lee , Jong-oh Kwon , Woon-bae Kim , Jea-shik Shin , Jun-sik Hwang , Eun-sung Lee
发明人： Moon-chul Lee , Jong-oh Kwon , Woon-bae Kim , Jea-shik Shin , Jun-sik Hwang , Eun-sung Lee
IPC分类号： H01F5/00 , H01L23/02
CPC分类号： H01F17/0006 , H01F41/041 , H01F2017/0046 , H01L27/08 , Y10T29/4902 , Y10T29/4906 , Y10T29/49064 , Y10T29/49073 , Y10T29/49155 , Y10T29/49165
摘要： An inductor embedded in a substrate, including a substrate, a coil electrode formed by filling a metal in a spiral hole formed on the substrate, an insulation layer formed on the substrate, and an external connection pad formed on the insulation layer to be connected to the coil electrode. The inductor-embedded substrate can be used as a cap for a micro device package by forming a cavity on its bottom surface.
摘要翻译：嵌入基板的电感器，包括基板，通过在形成在基板上的螺旋孔中填充金属而形成的线圈电极，形成在基板上的绝缘层，以及形成在绝缘层上的外部连接焊盘，以连接到线圈电极。电感器嵌入式基板可以通过在其底表面上形成空腔而用作微器件封装的帽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式