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1. 发明授权

US06723616B2 Process of increasing screen dielectric thickness 有权
标题翻译：屏幕介电厚度增加的过程
公开(公告)号：US06723616B2
公开(公告)日：2004-04-20
申请号：US10253870
申请日：2002-09-24
申请人： Seetharaman Sridhar , Youngmin Kim , Zhiqiang Wu , Mark S. Rodder
发明人： Seetharaman Sridhar , Youngmin Kim , Zhiqiang Wu , Mark S. Rodder
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method of forming a semiconductor device using shallow trench isolation, includes forming a trench within a semiconductor substrate and forming a screen dielectric stack outwardly from the semiconductor substrate. The screen dielectric stack includes a first sacrificial dielectric layer disposed outwardly from the semiconductor substrate and a second sacrificial dielectric layer disposed outwardly from and in contact with the first sacrificial dielectric layer. In one embodiment, the first sacrificial dielectric layer is formed before forming the trench and the second sacrificial dielectric layer is formed after forming the trench.
摘要翻译：使用浅沟槽隔离来形成半导体器件的方法包括在半导体衬底内形成沟槽并从半导体衬底向外形成屏蔽电介质堆叠。屏幕电介质堆叠包括从半导体衬底向外设置的第一牺牲电介质层和从第一牺牲介电层向外设置并与之接触的第二牺牲电介质层。在一个实施例中，在形成沟槽之前形成第一牺牲电介质层，并且在形成沟槽之后形成第二牺牲绝缘层。

2. 发明授权

US09153662B2 MOSFET with selective dopant deactivation underneath gate 有权
标题翻译：栅极下选择性掺杂剂失活的MOSFET
公开(公告)号：US09153662B2
公开(公告)日：2015-10-06
申请号：US13434630
申请日：2012-03-29
申请人： Dhanyakumar Mahaveer Sathaiya , Kai-Chieh Yang , Wei-Hao Wu , Ken-Ichi Goto , Zhiqiang Wu , Yuan-Chen Sun
发明人： Dhanyakumar Mahaveer Sathaiya , Kai-Chieh Yang , Wei-Hao Wu , Ken-Ichi Goto , Zhiqiang Wu , Yuan-Chen Sun
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L21/265
CPC分类号： H01L29/1041 , H01L21/26506 , H01L21/2658 , H01L29/1045 , H01L29/1608 , H01L29/66537 , H01L29/66545 , H01L29/66651 , H01L29/7833
摘要： A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device.
摘要翻译：在衬底上制造金属氧化物半导体场效应晶体管（MOSFET）器件的方法包括用第一类掺杂剂掺杂MOSFET器件的沟道区。源极和漏极在衬底中形成具有第二类型的掺杂剂。选择性掺杂剂失活在MOSFET器件的栅极下方的区域中进行。

3. 发明授权

US08859380B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08859380B2
公开(公告)日：2014-10-14
申请号：US12944104
申请日：2010-11-11
申请人： Zhiqiang Wu , Yi-Ming Sheu , Tsung-Hsing Yu , Kuan-Lun Cheng , Chih-Pin Tsao , Wen-Yuan Chen , Chun-Fu Cheng , Chih-Ching Wang
发明人： Zhiqiang Wu , Yi-Ming Sheu , Tsung-Hsing Yu , Kuan-Lun Cheng , Chih-Pin Tsao , Wen-Yuan Chen , Chun-Fu Cheng , Chih-Ching Wang
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823468 , H01L29/66492 , H01L29/66545 , H01L29/66575
摘要： A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°.
摘要翻译：形成集成电路的方法包括：在衬底上形成沿着第一方向纵向布置的多个栅极结构。对基板执行多个角度离子注入。每个角度离子注入相对于第二方向具有相应的注入角度。第二方向基本上平行于衬底的表面并且基本上与第一方向正交。每个注入角度基本上大于0°。

4. 发明授权

US08622677B2 Semi-trailer support loading nut 失效
标题翻译：半挂车支撑装载螺母
公开(公告)号：US08622677B2
公开(公告)日：2014-01-07
申请号：US12744153
申请日：2008-05-23
申请人： Zhiqiang Wu , Shaofan Zeng , Xiangyong Zhong
发明人： Zhiqiang Wu , Shaofan Zeng , Xiangyong Zhong
IPC分类号： F16B37/00
CPC分类号： B60S9/08
摘要： A semi-trailer leg loading nut includes a screwed hole provided on a nut column and connecting two ends of the nut. Said nut is a two-layered structure formed of a top layer and an under layer or a three-layered structure formed of a top layer, an intermediate layer and an under layer. The outer outline of at least two layers of the nut is a square with the same cutting angle. The side length of the two layers of squares is equal. The outer outline projection of the two layers of squares overlap with each other along the column axis direction. The outer outline projection of the other layer is within the overlapped projection of the two layers along the column axis direction. A funneled oil cup or an oil groove is provided on the top layer of the nut and communicates with the screwed hole. A bottom of the under layer of the nut is plane and is pressed on a loading plate in a quadrate pipe to transfer load.
摘要翻译：半挂车小腿装载螺母包括设在螺母柱上并连接螺母两端的螺纹孔。所述螺母是由顶层和下层或由顶层，中间层和下层形成的三层结构形成的两层结构。螺母的至少两层的外轮廓是具有相同切割角度的正方形。两层正方形的边长相等。两层正方形的外轮廓投影沿柱轴方向相互重叠。另一层的外轮廓投影在两列沿着列轴方向的重叠投影内。漏斗油杯或油槽设置在螺母的顶层上，并与螺纹孔连通。螺母底层的底部是平面的，并被压在方管中的装载板上以传递负载。

5. 发明授权

US08497171B1 FinFET method and structure with embedded underlying anti-punch through layer 有权
标题翻译： FinFET方法和结构具有嵌入式底层抗穿透层
公开(公告)号：US08497171B1
公开(公告)日：2013-07-30
申请号：US13541806
申请日：2012-07-05
申请人： Wei-Hao Wu , Kai-Chieh Yang , Wen-Hsing Hsieh , Ken-Ichi Goto , Zhiqiang Wu
发明人： Wei-Hao Wu , Kai-Chieh Yang , Wen-Hsing Hsieh , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823821
摘要： Methods and structures for forming semiconductor FinFET devices with superior repeatability and reliability include providing APT (anti-punch through) layer accurately formed beneath a semiconductor fins, are provided. Both the n-type and p-type APT layers are formed prior to the formation of the material from which the semiconductor fin is formed. In some embodiments, barrier layers are added between the accurately positioned APT layer and the semiconductor fin. Ion implantation methods and epitaxial growth methods are used to form appropriately doped APT layers in a semiconductor substrate surface. The fin material is formed over the APT layers using epitaxial growth/deposition methods.
摘要翻译：用于形成具有优异重复性和可靠性的半导体FinFET器件的方法和结构包括提供准确地形成在半导体鳍片之下的APT（抗穿通）层。在形成半导体翅片的材料形成之前，形成n型和p型APT层。在一些实施例中，在精确定位的APT层和半导体鳍片之间添加阻挡层。使用离子注入方法和外延生长方法在半导体衬底表面中形成适当掺杂的APT层。使用外延生长/沉积方法在APT层上形成翅片材料。

6. 发明申请

US20120056398A1 SEMI-TRAILER AXLE AND SUSPENSION CONNECTING STRUCTURE 审中-公开
标题翻译：半挂车轴和悬挂连接结构
公开(公告)号：US20120056398A1
公开(公告)日：2012-03-08
申请号：US13320543
申请日：2009-12-01
申请人： Zhiqiang Wu
发明人： Zhiqiang Wu
IPC分类号： B60G11/27 , B60G9/00
CPC分类号： B60G9/003 , B60G2202/152 , B60G2204/4306 , B60G2206/30
摘要： A semi-trailer axle and suspension connecting structure includes an axle (5), a suspension system and a connecting member arranged on the axle (5) body and a suspension support plate (6) of the suspension system. A locating structure is arranged on the match surface of the axle (5) and the suspension support plate (6) to prevent the circumferentially and axially relative displacement between the axle (5) and the suspension support plate (6). The invention omits a welding process for the axle body and the suspension support plate (6). The axle body still keeps a good strength structure while the firm connection of the axle body and the suspension arrives, and the stress damage caused by welding is avoided.
摘要翻译：半挂车轴和悬挂连接结构包括轴（5），悬架系统和布置在轴（5）主体上的连接构件和悬架系统的悬架支撑板（6）。定位结构布置在轴（5）和悬架支撑板（6）的匹配表面上，以防止轴（5）和悬架支撑板（6）之间的周向和轴向相对位移。本发明省略了用于车轴和悬架支撑板（6）的焊接工艺。轴体和悬架的牢固连接到达时，轴体仍保持良好的强度结构，避免了焊接引起的应力损伤。

7. 发明申请

US20110070703A1 Disposable Spacer Integration with Stress Memorization Technique and Silicon-Germanium 有权
标题翻译：一次性间隔与应力记忆技术和硅锗的整合
公开(公告)号：US20110070703A1
公开(公告)日：2011-03-24
申请号：US12549862
申请日：2009-08-28
申请人： Weize Xiong , Zhiqiang Wu , Xin Wang
发明人： Weize Xiong , Zhiqiang Wu , Xin Wang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).
摘要翻译：一种用于使用应力存储技术（SMT）层（126）形成NMOS晶体管（104）和嵌入式SiGe（eSiGe）PMOS晶体管（102）的集成工艺流程。 SMT层（126）沉积在NMOS晶体管（104）和PMOS晶体管（102）两者之上。在PMOS晶体管（102）上方的SMT层（126）的部分被各向异性蚀刻以形成间隔物（128），而不通过NMOS晶体管（104）蚀刻SMT层（126）的部分。间隔物（128）用于对准SiGe凹陷蚀刻和生长以形成SiGe源极/漏极区域（132）。在蚀刻SMT层（126）之后执行源极/漏极退火，使得SMT层（126）在不降低PMOS晶体管（102）的情况下向NMOS晶体管（104）提供期望的应力。

8. 发明授权

US07189602B2 Method and apparatus for reducing substrate bias voltage drop 有权
标题翻译：降低衬底偏置电压降的方法和装置
公开(公告)号：US07189602B2
公开(公告)日：2007-03-13
申请号：US09998165
申请日：2001-12-03
申请人： Tongbi Jiang , Zhiqiang Wu
发明人： Tongbi Jiang , Zhiqiang Wu
IPC分类号： H01L21/00
CPC分类号： H01L24/06 , H01L23/4827 , H01L23/4828 , H01L23/585 , H01L24/48 , H01L27/08 , H01L27/10882 , H01L27/10897 , H01L2223/665 , H01L2224/04042 , H01L2224/05093 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/8546 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device is provided with a conductive layer provided on a backside of a semiconductor substrate. The conductive layer helps maintain a uniform bias voltage over the substrate. The conductive layer can also be used to apply a bias voltage to the substrate and reduce the number of bias voltage distribution regions required.
摘要翻译：半导体器件设置有设置在半导体衬底的背面上的导电层。导电层有助于在衬底上保持均匀的偏置电压。导电层也可用于向衬底施加偏置电压并减少所需的偏置电压分布区域的数量。

9. 发明授权

US07118979B2 Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate electrode 有权
标题翻译：在多晶硅栅电极的侧壁上制造具有锗注入区的晶体管的方法
公开(公告)号：US07118979B2
公开(公告)日：2006-10-10
申请号：US10701818
申请日：2003-11-05
申请人： Kaiping Liu , Zhiqiang Wu , Majid Movahed Mansoorz
发明人： Kaiping Liu , Zhiqiang Wu , Majid Movahed Mansoorz
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/26506 , H01L21/26586 , H01L21/2807 , H01L21/28105 , H01L21/823828
摘要： The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.
摘要翻译：本发明提供一种具有位于其中的锗注入区域170的晶体管100及其制造方法，以及包括上述晶体管的集成电路。在一个实施例中，晶体管100包括位于半导体衬底110上方的多晶硅栅电极140，其中多晶硅栅电极140的侧壁上具有锗注入区170。晶体管100还包括靠近多晶硅栅电极140位于半导体衬底110内的源/漏区160。

10. 发明授权

US06875650B2 Eliminating substrate noise by an electrically isolated high-voltage I/O transistor 有权
标题翻译：通过电隔离的高压I / O晶体管消除衬底噪声
公开(公告)号：US06875650B2
公开(公告)日：2005-04-05
申请号：US10684948
申请日：2003-10-14
申请人： Craig T. Salling , Zhiqiang Wu
发明人： Craig T. Salling , Zhiqiang Wu
IPC分类号： H01L27/04 , H01L21/761 , H01L21/822 , H01L29/10 , H01L29/78 , H01L21/8238 , H01L21/336 , H01L21/425
CPC分类号： H01L29/1083 , H01L21/761 , H01L29/7833
摘要： On the surface of a semiconductor material of a first conductivity type 101a, a lateral MOS transistor 100 is described surrounded by a well 171 of the opposite conductivity type and, nested within the well, an electrical isolation region 102. The semiconductor region 101a embedding this transistor has a resistivity higher than the remainder of the semiconductor material 101 and further contains a buried layer 160 of the opposite conductivity type. This layer 160 extends laterally to the wells 171, thereby electrically isolating the near-surface portion of the semiconductor region from the remainder of the semiconductor material, and enabling the MOS transistor to operate as an electrically isolated high-voltage I/O transistor for circuit noise reduction, while having low drain junction capacitance.In the first embodiment of the invention (FIG. 1), the buried layer 171 extends vertically deeper from the surface than the electrical isolation region 102, thereby enabling a separate contact 106 to the electrically isolated near-surface portion 101a of the semiconductor region.
摘要翻译：在第一导电类型101a的半导体材料的表面上，横向MOS晶体管100被描述为由相反导电类型的阱171包围，并且嵌套在阱内的电隔离区域102.半导体区域101a嵌入该晶体管的电阻率高于半导体材料101的其余部分，并且还包含相反导电类型的掩埋层160。该层160横向延伸到阱171，从而将半导体区域的近表面部分与半导体材料的其余部分电绝缘，并且使MOS晶体管能够作为用于电路的电隔离的高压I / O晶体管工作噪声降低，同时具有低漏极结电容。在本发明的第一实施例（图1）中，掩埋层171从表面比电隔离区域102垂直地更深地延伸，从而使单独的触点106能够电隔离半导体区域的近表面部分101a。

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