专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07118979B2 Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate electrode 有权
标题翻译：在多晶硅栅电极的侧壁上制造具有锗注入区的晶体管的方法
公开(公告)号：US07118979B2
公开(公告)日：2006-10-10
申请号：US10701818
申请日：2003-11-05
申请人： Kaiping Liu , Zhiqiang Wu , Majid Movahed Mansoorz
发明人： Kaiping Liu , Zhiqiang Wu , Majid Movahed Mansoorz
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/26506 , H01L21/26586 , H01L21/2807 , H01L21/28105 , H01L21/823828
摘要： The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.
摘要翻译：本发明提供一种具有位于其中的锗注入区域170的晶体管100及其制造方法，以及包括上述晶体管的集成电路。在一个实施例中，晶体管100包括位于半导体衬底110上方的多晶硅栅电极140，其中多晶硅栅电极140的侧壁上具有锗注入区170。晶体管100还包括靠近多晶硅栅电极140位于半导体衬底110内的源/漏区160。

2. 发明申请

US20100022062A1 TRANSITOR HAVING A GERMANIUM IMPLANT REGION LOCATED THEREIN AND A METHOD OF MANUFACTURE THEREFOR 审中-公开
标题翻译：具有位于其中的德国植被区域的传送器及其制造方法
公开(公告)号：US20100022062A1
公开(公告)日：2010-01-28
申请号：US12573450
申请日：2009-10-05
申请人： Kaiping Liu , Zhiqiang Wu , Majid Movahed Mansoorz
发明人： Kaiping Liu , Zhiqiang Wu , Majid Movahed Mansoorz
IPC分类号： H01L21/265
CPC分类号： H01L21/26506 , H01L21/26586 , H01L21/2807 , H01L21/28105 , H01L21/823828 , H01L29/4983
摘要： The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.
摘要翻译：本发明提供一种具有位于其中的锗注入区域170的晶体管100及其制造方法，以及包括上述晶体管的集成电路。在一个实施例中，晶体管100包括位于半导体衬底110上方的多晶硅栅电极140，其中多晶硅栅电极140的侧壁上具有锗注入区170。晶体管100还包括靠近多晶硅栅电极140位于半导体衬底110内的源/漏区160。

3. 发明授权

US06727131B2 System and method for addressing junction capacitances in semiconductor devices 有权
标题翻译：用于解决半导体器件中的结电容的系统和方法
公开(公告)号：US06727131B2
公开(公告)日：2004-04-27
申请号：US10279650
申请日：2002-10-24
申请人： Zhiqiang Wu , Kaiping Liu
发明人： Zhiqiang Wu , Kaiping Liu
IPC分类号： H01L218238
CPC分类号： H01L21/26513 , H01L21/324 , H01L29/6659
摘要： A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a semiconductor substrate. The gate conductor defines a channel region disposed inwardly from the gate conductor. Source and drain regions are formed in the semiconductor substrate, each disposed adjacent one edge of the channel region. The semiconductor substrate and the source and drain regions have an associated bottom wall junction capacitance. A transient enhanced diffusion anneal is used to affect ion concentration profiles associated with the source and drain regions, resulting in an increased balance in the ion concentration profiles of the source and drain regions and an ion concentration associated with the semiconductor substrate, which results in reduction of the bottom wall junction capacitance.
摘要翻译：提供一种形成半导体器件的方法，其包括形成靠近并与半导体衬底的外表面绝缘的栅极导体。栅极导体限定了从栅极导体向内设置的沟道区。源极和漏极区域形成在半导体衬底中，每个设置在沟道区域的一个边缘附近。半导体衬底和源极和漏极区域具有相关联的底壁结电容。使用瞬时增强扩散退火来影响与源区和漏区相关的离子浓度分布，导致源区和漏区的离子浓度分布的增加平衡以及与半导体衬底相关联的离子浓度，这导致减少的底壁结电容。

4. 发明授权

US07038258B2 Semiconductor device having a localized halo implant therein and method of manufacture therefor 有权
标题翻译：具有局部晕轮植入物的半导体器件及其制造方法
公开(公告)号：US07038258B2
公开(公告)日：2006-05-02
申请号：US10913594
申请日：2004-08-05
申请人： Kaiping Liu , Zhiqiang Wu
发明人： Kaiping Liu , Zhiqiang Wu
IPC分类号： H01L27/148 , H01L21/336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/823807 , H01L29/66537 , H01L29/78
摘要： The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor device 200 includes a gate 244 located over a substrate 210, the substrate 210 having a source and a drain 230 located therein. In the same embodiment, located adjacent each of the source and drain 230 are localized halo implants 250, each of the localized halo implants 250 having a vertical implant region 260 and an angled implant region 265. Further, at an intersection of the vertical implant region 260 and the angled implant region 265 is an area of peak concentration.
摘要翻译：本发明提供一种半导体器件200，其具有位于其中的局部晕轮植入物250，因此制造方法以及包括该半导体器件的集成电路。在一个实施例中，半导体器件200包括位于衬底210上的栅极244，衬底210具有位于其中的源极和漏极230。在相同的实施例中，邻近源极和漏极230中的每一个定位的晕轮植入物250，每个局部晕轮植入物250具有垂直注入区域260和倾斜的注入区域265。此外，在垂直注入区域260和倾斜注入区域265的交点处是峰值浓度的区域。

5. 发明申请

US20050263897A1 Reducing the migration of grain boundaries 有权
公开(公告)号：US20050263897A1
公开(公告)日：2005-12-01
申请号：US11182929
申请日：2005-07-15
申请人： Kaiping Liu , Zhiqiang Wu , Jihong Chen
发明人： Kaiping Liu , Zhiqiang Wu , Jihong Chen
IPC分类号： H01L21/00 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/461 , H01L23/48 , H01L23/52 , H01L29/40 , H01L29/49
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

6. 发明申请

US20050012149A1 Semiconductor device having a localized halo implant therein and method of manufacture therefor 有权
标题翻译：具有局部晕轮植入物的半导体器件及其制造方法
公开(公告)号：US20050012149A1
公开(公告)日：2005-01-20
申请号：US10913594
申请日：2004-08-05
申请人： Kaiping Liu , Zhiqiang Wu
发明人： Kaiping Liu , Zhiqiang Wu
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L29/76 , H01L31/062
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/823807 , H01L29/66537 , H01L29/78
摘要： The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor device 200 includes a gate 244 located over a substrate 210, the substrate 210 having a source and a drain 230 located therein. In the same embodiment, located adjacent each of the source and drain 230 are localized halo implants 250, each of the localized halo implants 250 having a vertical implant region 260 and an angled implant region 265. Further, at an intersection of the vertical implant region 260 and the angled implant region 265 is an area of peak concentration.
摘要翻译：本发明提供一种半导体器件200，其具有位于其中的局部晕轮植入物250，因此制造方法以及包括该半导体器件的集成电路。在一个实施例中，半导体器件200包括位于衬底210上的栅极244，衬底210具有位于其中的源极和漏极230。在相同的实施例中，位于源极和漏极230的每一个附近的是局部晕轮注入250，每个局部晕轮植入物250具有垂直注入区域260和倾斜注入区域265.此外，在垂直注入区域 260和角度注入区域265是峰值浓度的区域。

7. 发明授权

US06955980B2 Reducing the migration of grain boundaries 有权
标题翻译：减少晶界迁移
公开(公告)号：US06955980B2
公开(公告)日：2005-10-18
申请号：US10233354
申请日：2002-08-30
申请人： Kaiping Liu , Zhiqiang Wu , Jihong Chen
发明人： Kaiping Liu , Zhiqiang Wu , Jihong Chen
IPC分类号： H01L21/00 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/461 , H01L23/48 , H01L23/52 , H01L29/40 , H01L29/49
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.
摘要翻译：形成半导体器件的方法包括将沉淀注入到至少部分形成的半导体器件的栅极导体中。栅极导体包括多个半导体晶粒。形成掺杂剂迁移路径的相邻晶粒的边界。在栅极导体内形成多个沉淀区。位于至少两个晶粒的结的至少一些沉淀区域。至少部分形成的半导体器件的栅极导体掺杂有掺杂剂。掺杂剂沿掺杂剂迁移路径向内扩散。

8. 发明授权

US06940137B2 Semiconductor device having an angled compensation implant and method of manufacture therefor 有权
标题翻译：具有倾斜补偿植入物的半导体器件及其制造方法
公开(公告)号：US06940137B2
公开(公告)日：2005-09-06
申请号：US10667012
申请日：2003-09-19
申请人： Jihong Chen , Zhiqiang Wu , Kaiping Liu
发明人： Jihong Chen , Zhiqiang Wu , Kaiping Liu
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/78 , H01L29/72
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/1083 , H01L29/7833
摘要： The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the angled compensation implant. In one embodiment, the method of manufacturing the semiconductor device 200 includes creating a halo implant 240 in a substrate 210, introducing a compensation implant 260 in the substrate 210 at an angle abnormal to the substrate 210 and forming a source/drain region 250 above the compensation implant 260, the angle reducing a capacitance associated with the halo implant 240 or the source/drain region 250. The method further includes placing a gate structure 230 over the substrate 210.
摘要翻译：本发明提供一种具有成角度的补偿植入物的半导体器件200，因此制造方法以及制造包括角度补偿植入物的集成电路的方法。在一个实施例中，制造半导体器件200的方法包括在衬底210中形成晕环植入物240，将衬底210中的补偿注入260以与衬底210成异角的方式引入补偿注入260，并在衬底210上方形成源/漏区250 补偿注入260，减小与晕轮植入物240或源极/漏极区域250相关联的电容的角度。该方法还包括将栅极结构230放置在衬底210上。

9. 发明申请

US20050062103A1 Semiconductor device having an angled compensation implant and method of manufacture therefor 有权
标题翻译：具有倾斜补偿植入物的半导体器件及其制造方法
公开(公告)号：US20050062103A1
公开(公告)日：2005-03-24
申请号：US10667012
申请日：2003-09-19
申请人： Jihong Chen , Zhiqiang Wu , Kaiping Liu
发明人： Jihong Chen , Zhiqiang Wu , Kaiping Liu
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/1083 , H01L29/7833
摘要： The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the angled compensation implant. In one embodiment, the method of manufacturing the semiconductor device 200 includes creating a halo implant 240 in a substrate 210, introducing a compensation implant 260 in the substrate 210 at an angle abnormal to the substrate 210 and forming a source/drain region 250 above the compensation implant 260, the angle reducing a capacitance associated with the halo implant 240 or the source/drain region 250. The method further includes placing a gate structure 230 over the substrate 210.
摘要翻译：本发明提供一种具有成角度的补偿植入物的半导体器件200，因此制造方法以及制造包括角度补偿植入物的集成电路的方法。在一个实施例中，制造半导体器件200的方法包括在衬底210中形成晕环植入物240，将衬底210中的补偿注入260以与衬底210成异角的方式引入补偿注入260，并在衬底210上方形成源/漏区250 补偿注入260，该角度减小与晕轮植入物240或源极/漏极区域250相关联的电容。该方法还包括将栅极结构230放置在衬底210上方。

10. 发明授权

US06713360B2 System for reducing segregation and diffusion of halo implants into highly doped regions 有权
标题翻译：用于减少晕轮植入物到高掺杂区域的偏析和扩散的系统
公开(公告)号：US06713360B2
公开(公告)日：2004-03-30
申请号：US10218027
申请日：2002-08-12
申请人： Amitabh Jain , Kaiping Liu , Zhiqiang Wu
发明人： Amitabh Jain , Kaiping Liu , Zhiqiang Wu
IPC分类号： H01L21331
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L29/1083
摘要： The present invention provides a method for forming a transistor junction in a semiconductor wafer by implanting a dopant material (116) into the semiconductor wafer, implanting a halo material (110) into the semiconductor wafer (102), selecting a fluorine dose and energy to tailor one or more characteristics of the transistor, implanting fluorine into the semiconductor wafer at the selected dose and energy, activating the dopant material using a thermal process and annealing the semiconductor wafer to remove residual fluorine. The one or more characteristics of the transistor may include halo segregation, halo diffusion, the sharpness of the halo profile, dopant activation, dopant profile sharpness, drive current, bottom wall capacitance or near edge capacitance.
摘要翻译：本发明提供了一种通过将掺杂剂材料（116）注入到半导体晶片中而在半导体晶片中形成晶体管结的方法，将卤素材料（110）注入到半导体晶片（102）中，选择氟剂量和能量定制晶体管的一个或多个特性，以选择的剂量和能量将氟注入到半导体晶片中，使用热处理激活掺杂剂材料并退火半导体晶片以除去残留的氟。晶体管的一个或多个特性可以包括卤素偏析，卤素扩散，晕轮廓的锐度，掺杂剂激活，掺杂剂分布锐度，驱动电流，底壁电容或近边缘电容。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式