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1. 发明授权

US5586078A Dynamic type memory 失效
标题翻译：动态类型内存
公开(公告)号：US5586078A
公开(公告)日：1996-12-17
申请号：US528306
申请日：1995-09-14
申请人： Satoru Takase , Kiyofumi Sakurai , Masaki Ogihara
发明人： Satoru Takase , Kiyofumi Sakurai , Masaki Ogihara
IPC分类号： G11C11/401 , G06F12/08 , G11C11/409 , G11C11/4091 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G06F12/0893 , G11C11/4091 , G11C11/4096
摘要： A DRAM includes memory blocks in a form of division of shared sense amplifier configuration in which sub arrays and sense amplifiers serving as cache memories are alternately arranged in the X direction of a memory chip. The memory blocks are arranged in the Y direction. Data lines are formed in parallel with the Y direction for the corresponding sub arrays, for transferring data held in the sense amplifiers corresponding to the sub arrays. I/O pads are arranged in parallel with the X direction, for inputting/outputting data to/from the corresponding sub arrays via the data lines. When the shared sense amplifier configuration and sense amplifier cache system are achieved in a small area of the DRAM, the hit rate of the cache memories is increased, and data can be transferred at high speed by shortening data paths formed in the memory chip.
摘要翻译： DRAM包括以共享读出放大器配置划分的形式的存储器块，其中用作高速缓冲存储器的子阵列和读出放大器在存储器芯片的X方向上交替排列。存储块沿Y方向排列。数据线与对应的子阵列的Y方向平行地形成，用于传送保持在与子阵列相对应的读出放大器中的数据。 I / O焊盘与X方向平行布置，用于经由数据线向/从相应的子阵列输入/输出数据。当在DRAM的小区域中实现共享读出放大器配置和读出放大器缓存系统时，高速缓冲存储器的命中率增加，并且可以通过缩短存储芯片中形成的数据路径来高速传输数据。

2. 发明授权

US5712827A Dynamic type memory 失效
标题翻译：动态类型内存
公开(公告)号：US5712827A
公开(公告)日：1998-01-27
申请号：US530725
申请日：1995-09-19
申请人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
发明人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
IPC分类号： G11C11/401 , G11C5/02 , G11C7/06 , G11C7/10 , G11C11/409 , G11C11/4093 , G11C11/4096 , G11C13/00 , G11C11/34
CPC分类号： G11C7/1012 , G11C11/4093 , G11C11/4096 , G11C5/025 , G11C7/06 , G11C7/10 , G11C7/1006
摘要： In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.
摘要翻译：在动态类型存储器中，存储器单元阵列被划分成存储器芯片上的多个子阵列。每个子阵列设置有与字线并行形成的数据线。数据缓冲器和多路复用器电路和I / O焊盘与位线并行布置在存储器芯片的一侧。这种布置允许数据路径被缩短并且能够高速传送数据。

3. 再颁专利

USRE37427E1 Dynamic type memory 有权
标题翻译：动态类型内存
公开(公告)号：USRE37427E1
公开(公告)日：2001-10-30
申请号：US09493001
申请日：2000-01-27
申请人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
发明人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
IPC分类号： G11C1300
CPC分类号： G11C7/1012 , G11C5/025 , G11C7/06 , G11C7/10 , G11C7/1006 , G11C11/4093 , G11C11/4096
摘要： In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.
摘要翻译：在动态类型存储器中，存储器单元阵列被划分成存储器芯片上的多个子阵列。每个子阵列设置有与字线并行形成的数据线。数据缓冲器和多路复用器电路和I / O焊盘与位线并行布置在存储器芯片的一侧。这种布置允许数据路径被缩短并且能够高速传送数据。

4. 发明授权

US5642326A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US5642326A
公开(公告)日：1997-06-24
申请号：US534558
申请日：1995-09-27
申请人： Kiyofumi Sakurai , Satoru Takase , Masaki Ogihara
发明人： Kiyofumi Sakurai , Satoru Takase , Masaki Ogihara
IPC分类号： G11C11/407 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/409 , G11C7/00
CPC分类号： G11C11/4076 , G11C7/22 , G11C8/18
摘要： A dynamic memory comprises a control circuit for controlling the selection of the row decoder and the activation of the sense amplifiers in accordance with a RAS signal externally supplied thereto and a word line control circuit for controlling a selected word line to turn the electric potentials read out from the memory cells connected to the word line on the bit lines connected to the respective memory cells back to an inactive level after the electric potentials are sensed and amplified by the sense amplifiers corresponding to the respective bit lines during the time period from the time when the RAS signal is turned to an active level and the time when it is turned back to the inactive level. A dynamic memory has gate oxide films are designed to be subjected to a less electric field strength in order to minimize the degradation of reliability and the memory can effectively reduce the fall of the word line driving stepped-up voltage to eliminate the necessity of a leak current compensation circuit. Additionally, the memory reduces the time required to restore the electric potentials for a data reading operation and also the cycle time required for a data writing operation.
摘要翻译：动态存储器包括控制电路，用于根据外部提供给它的+ E，ovs RAS + EE信号和用于控制选定字线的字线控制电路来控制行解码器的选择和感测放大器的激活将连接到各个存储器单元的位线上连接到字线的存储单元读出的电位在由该位线对应的读出放大器在从+ E，ovs RAS + EE信号变为有效电平的时间段和其回到无效电平的时间。具有栅极氧化膜的动态存储器被设计为经受较少的电场强度以便最小化可靠性的劣化，并且存储器可以有效地减少字线驱动升压电压的下降以消除泄漏的必要性电流补偿电路。此外，存储器减少了恢复数据读取操作的电位所需的时间以及数据写入操作所需的周期时间。

5. 发明授权

US5335205A DRAM using word line potential control circuitcircuit 失效
标题翻译： DRAM采用字线电位控制电路
公开(公告)号：US5335205A
公开(公告)日：1994-08-02
申请号：US757632
申请日：1991-09-11
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G11C11/407 , G11C8/08 , G11C11/4074 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4074 , G11C11/4085 , G11C11/4087
摘要： Memory, cells includes at least one memory cell having an n-channel MOS transistor and an n-channel MOS capacitor. A word line is connected to the memory cells. A word line drive circuit for driving the word line includes a p-channel MOS transistor for transferring a potential to the word line. The word line drive circuit is controlled by an output from a word line potential control circuit. The word line potential control circuit applies a power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are not selected, and the word line potential control circuit applies a potential higher than a potential obtained by adding a threshold voltage of the n-channel MOS transistor to the power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are selected.
摘要翻译：存储器单元包括至少一个具有n沟道MOS晶体管和n沟道MOS电容器的存储单元。字线连接到存储单元。用于驱动字线的字线驱动电路包括用于将电位传送到字线的p沟道MOS晶体管。字线驱动电路由字线电位控制电路的输出控制。当没有选择存储单元时，字线电位控制电路通过字线驱动电路中的p沟道MOS晶体管的电流路径向字线施加电源电位，并且字线电位控制电路施加电位高于通过在选择存储单元时通过字线驱动电路中的p沟道MOS晶体管的电流路径将n沟道MOS晶体管的阈值电压加到字线而获得的电位。

6. 发明授权

US4931992A Semiconductor memory having barrier transistors connected between sense and restore circuits 失效
标题翻译：半导体存储器具有连接在感测和恢复电路之间的阻挡晶体管
公开(公告)号：US4931992A
公开(公告)日：1990-06-05
申请号：US310020
申请日：1989-02-09
申请人： Masaki Ogihara , Yoshio Okada , Syuso Fujii
发明人： Masaki Ogihara , Yoshio Okada , Syuso Fujii
IPC分类号： G11C11/4094
CPC分类号： G11C11/4094
摘要： A semiconductor memory comprises a memory cell for storing data, a bit line pair for transfering the data, a sense amplifier for amplifying the data from the bit line pair, a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory, and a pair of constant voltage barrier transistors connected between the restore circuit and the sense amplifier for increasing the speed of sensing.
摘要翻译：半导体存储器包括用于存储数据的存储单元，用于传送数据的位线对，用于放大来自位线对的数据的读出放大器，直接连接到位线对的恢复电路，用于恢复半导体中的数据存储器和连接在恢复电路和读出放大器之间的一对恒定电压势垒晶体管，用于增加感测速度。

7. 发明授权

US4829483A Method and apparatus for selecting disconnecting first and second bit line pairs for sensing data output from a drain at a high speed 失效
标题翻译：用于选择断开第一和第二位线对以便高速地从排水管输出的数据的方法和装置
公开(公告)号：US4829483A
公开(公告)日：1989-05-09
申请号：US128779
申请日：1987-12-04
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G11C11/409 , G11C7/10 , G11C7/12 , G11C11/4096
CPC分类号： G11C7/12 , G11C11/4096 , G11C7/1006
摘要： A dynamic semiconductor memory apparatus which can sense data at high speed includes first and second bit line pairs, memory cells connected to the first bit line pair, barrier transistors connected between the first and second bit line pairs, and a control unit for outputting a first control signal to the barrier transistors and for controlling transmission of a potential difference generated in the first bit line pair due to data read out from the memory cells to the second bit line pair in accordance with an input read control signal. The first control signal is at a first level for a first predetermined time interval after the read control signal is input, at a second level for a second predetermined time interval after the first predetermined time interval has passed, and at the first level after the second predetermined time interval has passed. An impedance of the barrier transistors obtained when the first control signal is at the first level is smaller than that obtained when the control signal is at the second level.
摘要翻译：可高速检测数据的动态半导体存储装置包括第一和第二位线对，连接到第一位线对的存储单元，连接在第一和第二位线对之间的阻挡晶体管，以及控制单元，用于输出第一位线对控制信号到所述阻挡晶体管并且用于控制由于根据输入的读控制信号从所述存储器单元读出到所述第二位线对的数据而在所述第一位线对中产生的电势差的传输。第一控制信号在读控制信号被输入之后的第一预定时间间隔处于第一电平，在经过第一预定时间间隔之后的第二预定时间间隔处于第二电平，并且在第二电平之后处于第二电平预定的时间间隔已过。当第一控制信号处于第一电平时获得的阻挡晶体管的阻抗小于当控制信号处于第二电平时获得的阻挡晶体管的阻抗。

8. 发明授权

US5550504A Dram using word line potential control circuit 失效
标题翻译：使用字线电位控制电路
公开(公告)号：US5550504A
公开(公告)日：1996-08-27
申请号：US240368
申请日：1994-05-10
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G11C11/407 , G11C8/08 , G11C11/4074 , G11C11/408 , G05F3/16 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4074 , G11C11/4085 , G11C11/4087
摘要： Memory cells includes at least one memory cell having an n-channel MOS transistor and an n-channel MOS capacitor. A word line is connected to the memory cells. A word line drive circuit for driving the word line includes a p-channel MOS transistor for transferring a potential to the word line. The word line drive circuit is controlled by an output from a word line potential control circuit. The word line potential control circuit applies a power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are not selected, and the word line potential control circuit applies a potential higher than a potential obtained by adding a threshold voltage of the n-channel MOS transistor to the power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are selected.
摘要翻译：存储单元包括具有n沟道MOS晶体管和n沟道MOS电容器的至少一个存储单元。字线连接到存储单元。用于驱动字线的字线驱动电路包括用于将电位传送到字线的p沟道MOS晶体管。字线驱动电路由字线电位控制电路的输出控制。当没有选择存储单元时，字线电位控制电路通过字线驱动电路中的p沟道MOS晶体管的电流路径向字线施加电源电位，并且字线电位控制电路施加电位高于通过在选择存储单元时通过字线驱动电路中的p沟道MOS晶体管的电流路径将n沟道MOS晶体管的阈值电压加到字线而获得的电位。

9. 发明授权

US5371710A Semiconductor memory device having test mode 失效
标题翻译：具有测试模式的半导体存储器件
公开(公告)号：US5371710A
公开(公告)日：1994-12-06
申请号：US46799
申请日：1993-04-16
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G11C29/00 , G11C8/12 , G11C11/401 , G11C11/407 , G11C29/06 , G11C29/34 , G11C29/46 , G11C29/50 , G11C13/00
CPC分类号： G11C29/50 , G11C29/34 , G11C29/46 , G11C8/12 , G11C11/401
摘要： A memory cell array, which is one of a plurality of divisional memory cell arrays, is selected by an address signal. One of the word lines incorporated in the memory cell array is selected by a row decoder. An OR circuit is supplied with a control signal for setting a burn-in test mode, and with the address signal for selecting the memory cell array. In the burn-in test mode, since the level of the control signal becomes high, the output level of the OR circuit becomes high irrespective of the address signal. Thus, the overall memory cell arrays are simultaneously selected, and hence more word lines than those accessed in a normal operation mode are simultaneously accessed.
摘要翻译：作为多个分割存储单元阵列之一的存储单元阵列由地址信号选择。结合在存储单元阵列中的字线之一由行解码器选择。 OR电路具有用于设置老化测试模式的控制信号，以及用于选择存储单元阵列的地址信号。在老化测试模式中，由于控制信号的电平变高，所以与电路信号无关，OR电路的输出电平变高。因此，同时选择整个存储单元阵列，因此与正常操作模式下访问的字线相比更多的字线被同时访问。

10. 发明授权

US5238860A Semiconductor device having different impurity concentration wells 失效
公开(公告)号：US5238860A
公开(公告)日：1993-08-24
申请号：US816565
申请日：1992-01-03
申请人： Shizuo Sawada , Syuso Fujii , Masaki Ogihara
发明人： Shizuo Sawada , Syuso Fujii , Masaki Ogihara
IPC分类号： H01L21/8234 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10808 , H01L21/823493 , H01L27/10829 , H01L27/105 , H01L2924/0002
摘要： A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.

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