专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5233558A Semiconductor memory device capable of directly reading the potential of bit lines 失效
标题翻译：能直接读取位线潜力的半导体存储器件
公开(公告)号：US5233558A
公开(公告)日：1993-08-03
申请号：US805965
申请日：1991-12-12
申请人： Syuso Fujii , Takeshi Nagai
发明人： Syuso Fujii , Takeshi Nagai
IPC分类号： G11C11/409 , G11C7/10 , G11C11/4091 , G11C11/4096 , G11C11/417
CPC分类号： G11C11/4096 , G11C11/4091 , G11C7/1006
摘要： Memory cell arrays containing dynamic memory cells and write/read circuits for these memory cell arrays are arranged alternately. In the write/read circuit, read amplifiers are provided at a rate of one for every four columns (bit line pairs). This read amplifier is composed of a preamplifier and a main amplifier. Each column is provided with a multiplexer, which selects a column and connects it to the preamplifier of a read amplifier. The signal amplified by this preamplifier is supplied to the main amplifier. The current-mirror load circuit of this main amplifier is in common use by a plurality of read amplifiers.

2. 发明授权

US5019729A TTL to CMOS buffer circuit 失效
标题翻译： TTL到CMOS缓冲电路
公开(公告)号：US5019729A
公开(公告)日：1991-05-28
申请号：US382493
申请日：1989-07-21
申请人： Tohru Kimura , Syuso Fujii , Takashi Ohsawa
发明人： Tohru Kimura , Syuso Fujii , Takashi Ohsawa
IPC分类号： G11C11/409 , H03K19/0185
CPC分类号： H03K19/018528 , H03K19/01855
摘要： A buffer circuit includes first and second differential amplification type buffer circuits. The input nodes of the first and second differential amplification type buffer circuits are connected together and the output nodes of the first and second differential amplification type buffer circuits are also connected to each other. The first differential amplification type buffer circuit is constituted by a pair of driving P-channel MOS transistors and N-channel MOS transistors acting as loads of the P-channel MOS transistors and connected to constitute a current mirror circuit. The second differential amplification type buffer circuit is constituted by P-channel MOS transistors acting as loads and connected to constitute a current mirror circuit and a pair of driving N-channel MOS transistors.
摘要翻译：缓冲电路包括第一和第二差分放大型缓冲电路。第一和第二差分放大型缓冲电路的输入节点连接在一起，并且第一和第二差分放大型缓冲电路的输出节点也彼此连接。第一差分放大型缓冲电路由作为P沟道MOS晶体管的负载的一对驱动P沟道MOS晶体管和N沟道MOS晶体管构成，并连接构成电流镜电路。第二差分放大型缓冲电路由作为负载的P沟道MOS晶体管构成，并连接构成电流镜电路和一对驱动N沟道MOS晶体管。

3. 发明授权

US4994874A Input protection circuit for semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的输入保护电路
公开(公告)号：US4994874A
公开(公告)日：1991-02-19
申请号：US425950
申请日：1989-10-24
申请人： Mitsuru Shimizu , Yoshio Okada , Syuso Fujii , Shozo Saito
发明人： Mitsuru Shimizu , Yoshio Okada , Syuso Fujii , Shozo Saito
IPC分类号： H01L27/04 , H01L21/822 , H01L23/60 , H01L27/02
CPC分类号： H01L27/0259
摘要： First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad. The first impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the first and third impurity regions constitute a first bipolar transistor for input protection and the second impurity region, the third impurity region and that portion of the P-type semiconductor substrate or P-well region which lies between the second and third impurity regions constitute a second bipolar transistor for input protection. The resistor and the first and second bipolar transistors constitute an input protection circuit.
摘要翻译：在N型半导体衬底中形成的P型半导体衬底或P阱区域的表面区域中，第一至第三N +型杂质区彼此分开地预定距离地形成。第一杂质区域连接到电源，第二杂质区域连接到接地端子。形成在第一和第二杂质区域之间的第三杂质区域连接到另一端连接到信号输入焊盘的输入保护电阻器的一端。位于第一和第三杂质区域之间的第一杂质区域，第三杂质区域和P型半导体衬底或P阱区域的部分构成用于输入保护的第一双极晶体管，第二杂质区域，第三杂质区域位于第二和第三杂质区之间的P型半导体衬底或P阱区的部分构成用于输入保护的第二双极晶体管。电阻器和第一和第二双极晶体管构成输入保护电路。

4. 发明授权

US4941031A Dynamic memory device with improved wiring layer layout 失效
标题翻译：具有改进布线层布局的动态存储器件
公开(公告)号：US4941031A
公开(公告)日：1990-07-10
申请号：US416604
申请日：1989-10-03
申请人： Jumpei Kumagai , Syuso Fujii
发明人： Jumpei Kumagai , Syuso Fujii
IPC分类号： G11C11/401 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108
CPC分类号： H01L27/0207 , G11C11/4097 , H01L27/10805 , H01L2924/0002 , Y10S257/922
摘要： A signal line runs in parallel with first to fourth bit lines on a memory cell array of a dynamic memory device. The signal line runs between and along the first and third bit lines, turns at a predetermined position, turns again and runs between and along the second and fourth bit lines. The predetermined turning position is a position corresponding to the half of the bit line length. The result is that the stray capacitances between the signal line and these bit lines are equal at about 1/2C.sub.F.

5. 发明授权

US4931992A Semiconductor memory having barrier transistors connected between sense and restore circuits 失效
标题翻译：半导体存储器具有连接在感测和恢复电路之间的阻挡晶体管
公开(公告)号：US4931992A
公开(公告)日：1990-06-05
申请号：US310020
申请日：1989-02-09
申请人： Masaki Ogihara , Yoshio Okada , Syuso Fujii
发明人： Masaki Ogihara , Yoshio Okada , Syuso Fujii
IPC分类号： G11C11/4094
CPC分类号： G11C11/4094
摘要： A semiconductor memory comprises a memory cell for storing data, a bit line pair for transfering the data, a sense amplifier for amplifying the data from the bit line pair, a restore circuit directly connected to the bit line pair for restoring the data in the semiconductor memory, and a pair of constant voltage barrier transistors connected between the restore circuit and the sense amplifier for increasing the speed of sensing.
摘要翻译：半导体存储器包括用于存储数据的存储单元，用于传送数据的位线对，用于放大来自位线对的数据的读出放大器，直接连接到位线对的恢复电路，用于恢复半导体中的数据存储器和连接在恢复电路和读出放大器之间的一对恒定电压势垒晶体管，用于增加感测速度。

6. 发明授权

US5420816A Semiconductor memory apparatus with configured word lines to reduce noise 失效
标题翻译：具有配置字线以减少噪声的半导体存储器件
公开(公告)号：US5420816A
公开(公告)日：1995-05-30
申请号：US299086
申请日：1994-08-31
申请人： Masaki Ogihara , Syuso Fujii
发明人： Masaki Ogihara , Syuso Fujii
IPC分类号： G11C11/407 , G11C8/14 , G11C11/401 , G11C5/06
CPC分类号： G11C8/14
摘要： According to this invention, a semiconductor apparatus includes a word line group consisting of four word lines, a bit line pair group, word line drive circuits, arrangement patterns of which are alternately inverted, for outputting boosted word line signals to the word line group, and memory contact portions provided to the bit line pair group in a 1/4-pitch system, wherein output terminals of the word line drive circuit having an inverted arrangement pattern are connected to memory cells so as to be aligned in the same order as in output terminals of the word line drive circuit having a non-inverted arrangement pattern.
摘要翻译：根据本发明，半导体装置包括由四个字线组成的字线组，位线对组，字线驱动电路，交替反转的排列图案，用于将升压的字线信号输出到字线组，以及以1/4间距系统提供给位线对组的存储器接触部分，其中具有反向排列图案的字线驱动电路的输出端子连接到存储器单元，以便按照与字线驱动电路的输出端子具有非反相布置图案。

7. 发明授权

US5066997A Semiconductor device 失效
公开(公告)号：US5066997A
公开(公告)日：1991-11-19
申请号：US436646
申请日：1989-11-15
申请人： Kiyofumi Sakurai , Syuso Fujii , Mitsuru Shimizu
发明人： Kiyofumi Sakurai , Syuso Fujii , Mitsuru Shimizu
IPC分类号： H01L21/3205 , G11C5/06 , G11C11/401 , H01L21/822 , H01L23/52 , H01L23/528 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L23/5283 , G11C5/063 , H01L27/108 , H01L2924/0002
摘要： A semiconductor device comprises a semiconductor chip and a memory array constituted by a plurality of memory blocks formed in the semiconductor chip and each having the essentially same construction and a plurality of bit lines arranged in columns at a predetermined interval. The semiconductor device further comprises a dummy wiring pattern arranged ajacent to the memory array in the semiconductor chip and including a dummy wiring layer set apart from outermost bit lines of each memory block a distance equal to the predetermined interval.

8. 发明授权

US5016224A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5016224A
公开(公告)日：1991-05-14
申请号：US404421
申请日：1989-09-08
申请人： Hiroto Tanaka , Syuso Fujii
发明人： Hiroto Tanaka , Syuso Fujii
IPC分类号： G11C11/401 , G11C7/06 , G11C11/4091 , G11C11/4097
CPC分类号： G11C7/06 , G11C11/4091 , G11C11/4097
摘要： First sense amplifiers formed of N-channel transistors are disposed between first and second memory cell blocks. Second sense amplifiers formed of P-channel transistors are disposed between second and third memory cell blocks. Switching transistors are disposed between the sense amplifiers and the memory cell blocks in order to select a particular memory cell block in response to signals applied to the gates thereof.
摘要翻译：由N沟道晶体管形成的第一读出放大器设置在第一和第二存储单元块之间。由P沟道晶体管形成的第二感测放大器设置在第二和第三存储单元块之间。开关晶体管设置在感测放大器和存储器单元块之间，以便响应于施加到其栅极的信号来选择特定存储器单元块。

9. 发明授权

US4896055A Semiconductor integrated circuit technology for eliminating circuits or arrays having abnormal operating characteristics 失效
标题翻译：用于消除具有异常工作特性的电路或阵列的半导体集成电路技术
公开(公告)号：US4896055A
公开(公告)日：1990-01-23
申请号：US164407
申请日：1988-03-04
申请人： Syuso Fujii , Shozo Saito
发明人： Syuso Fujii , Shozo Saito
IPC分类号： H01L21/82 , G01R31/3185 , G11C29/00 , H01L21/3205 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L27/10 , H03K19/003
CPC分类号： G11C29/70 , G01R31/318505 , G01R31/318511 , G01R31/318516 , G11C29/006 , G11C29/78 , G11C29/832
摘要： In a semiconductor integrated circuit, power lines or ground lines of a plurality of circuit blocks having equivalent functions are coupled via a switch circuit to a common main power line or main ground line on a semiconductor integrated circuit chip or semiconductor wafer. The main power line is supplied with power source potential and said main ground line with ground potential. A switch control circuit selectively switches the switch circuit ON or OFF so that defective circuit blocks may be deactivated.

10. 发明授权

US4769792A Semiconductor memory device with voltage bootstrap 失效
标题翻译：具有电压自举的半导体存储器件
公开(公告)号：US4769792A
公开(公告)日：1988-09-06
申请号：US923958
申请日：1986-10-28
申请人： Kazutaka Nogami , Takayasu Sakurai , Syuso Fujii
发明人： Kazutaka Nogami , Takayasu Sakurai , Syuso Fujii
IPC分类号： G11C5/14 , G11C7/12 , G11C8/08 , G11C11/406 , G11C11/40 , G11C13/00
CPC分类号： G11C7/12 , G11C11/406 , G11C5/145 , G11C8/08
摘要： Two or more voltage bootstrap circuits are included, and are sequentially operated. A continuous data write/read operation can be performed at a high speed. One of the two voltage bootstrap circuits is used for the data write/read operation and the other thereof is used for the refresh operation, thereby shortening the time required for refreshing.
摘要翻译：包括两个或多个电压自举电路，并且被依次操作。可以高速执行连续的数据写入/读取操作。两个电压自举电路中的一个用于数据写入/读取操作，另一个用于刷新操作，从而缩短刷新所需的时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式