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1. 发明授权

US07182257B2 Distribution management method and system 失效
标题翻译：分销管理方法和制度
公开(公告)号：US07182257B2
公开(公告)日：2007-02-27
申请号：US11090803
申请日：2005-03-24
申请人： Masaki Ogihara , Yasuhiko Mizuno , Rei Itsuki
发明人： Masaki Ogihara , Yasuhiko Mizuno , Rei Itsuki
IPC分类号： G06F17/60
CPC分类号： G06Q10/08
摘要： In one embodiment, a product distribution management system includes a product management center. The product management center includes a management device to receive product security data on a product from a distribution site and a product management database to store the data received from the distribution site for use in a product authentication process. The data includes product identification information and security information used to authenticate the product.
摘要翻译：在一个实施例中，产品分发管理系统包括产品管理中心。产品管理中心包括管理设备，用于从分发站点和产品管理数据库接收产品上的产品安全数据，以存储从分发站点接收的数据，以用于产品认证过程。数据包括用于认证产品的产品标识信息和安全信息。

2. 发明授权

US06880753B2 Distribution management method and system 失效
公开(公告)号：US06880753B2
公开(公告)日：2005-04-19
申请号：US10222956
申请日：2002-08-15
申请人： Masaki Ogihara , Yasuhiko Mizuno , Rei Itsuki
发明人： Masaki Ogihara , Yasuhiko Mizuno , Rei Itsuki
IPC分类号： B65G61/00 , G06K17/00 , G06K19/00 , G06Q10/08 , G06Q50/00 , G06Q50/28 , G06F17/60
CPC分类号： G06Q10/08
摘要： In one embodiment, a product distribution management system includes a product management center. The product management center includes a management device to receive product security data on a product from a distribution site and a product management database to store the data received from the distribution site for use in a product authentication process. The data includes product identification information and security information used to authenticate the product.

3. 再颁专利

USRE37427E1 Dynamic type memory 有权
标题翻译：动态类型内存
公开(公告)号：USRE37427E1
公开(公告)日：2001-10-30
申请号：US09493001
申请日：2000-01-27
申请人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
发明人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
IPC分类号： G11C1300
CPC分类号： G11C7/1012 , G11C5/025 , G11C7/06 , G11C7/10 , G11C7/1006 , G11C11/4093 , G11C11/4096
摘要： In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.
摘要翻译：在动态类型存储器中，存储器单元阵列被划分成存储器芯片上的多个子阵列。每个子阵列设置有与字线并行形成的数据线。数据缓冲器和多路复用器电路和I / O焊盘与位线并行布置在存储器芯片的一侧。这种布置允许数据路径被缩短并且能够高速传送数据。

4. 发明授权

US5642326A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US5642326A
公开(公告)日：1997-06-24
申请号：US534558
申请日：1995-09-27
申请人： Kiyofumi Sakurai , Satoru Takase , Masaki Ogihara
发明人： Kiyofumi Sakurai , Satoru Takase , Masaki Ogihara
IPC分类号： G11C11/407 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/409 , G11C7/00
CPC分类号： G11C11/4076 , G11C7/22 , G11C8/18
摘要： A dynamic memory comprises a control circuit for controlling the selection of the row decoder and the activation of the sense amplifiers in accordance with a RAS signal externally supplied thereto and a word line control circuit for controlling a selected word line to turn the electric potentials read out from the memory cells connected to the word line on the bit lines connected to the respective memory cells back to an inactive level after the electric potentials are sensed and amplified by the sense amplifiers corresponding to the respective bit lines during the time period from the time when the RAS signal is turned to an active level and the time when it is turned back to the inactive level. A dynamic memory has gate oxide films are designed to be subjected to a less electric field strength in order to minimize the degradation of reliability and the memory can effectively reduce the fall of the word line driving stepped-up voltage to eliminate the necessity of a leak current compensation circuit. Additionally, the memory reduces the time required to restore the electric potentials for a data reading operation and also the cycle time required for a data writing operation.
摘要翻译：动态存储器包括控制电路，用于根据外部提供给它的+ E，ovs RAS + EE信号和用于控制选定字线的字线控制电路来控制行解码器的选择和感测放大器的激活将连接到各个存储器单元的位线上连接到字线的存储单元读出的电位在由该位线对应的读出放大器在从+ E，ovs RAS + EE信号变为有效电平的时间段和其回到无效电平的时间。具有栅极氧化膜的动态存储器被设计为经受较少的电场强度以便最小化可靠性的劣化，并且存储器可以有效地减少字线驱动升压电压的下降以消除泄漏的必要性电流补偿电路。此外，存储器减少了恢复数据读取操作的电位所需的时间以及数据写入操作所需的周期时间。

5. 发明授权

US5633827A Semiconductor integrated circuit device allowing change of product specification and chip screening method therewith 失效
标题翻译：半导体集成电路器件允许改变产品规格和芯片筛选方法
公开(公告)号：US5633827A
公开(公告)日：1997-05-27
申请号：US435661
申请日：1995-05-05
申请人： Kenji Numata , Masaki Ogihara
发明人： Kenji Numata , Masaki Ogihara
IPC分类号： G11C11/406 , G11C5/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/44 , G11C29/50 , G11C29/56 , H01L27/10 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C29/028 , G11C29/44 , G11C29/50 , G11C29/50016 , G11C5/00 , G11C5/06 , G11C7/1018 , G11C11/401
摘要： A semiconductor integrated circuit device capable of changing the product specification. The semiconductor integrated circuit device comprises an integrated circuit section containing a first circuit section having a first function and a second circuit section having a second function, and active signal generator means for producing an active signal for activating the first circuit section or the second circuit section. To change the product specification, the integrated circuit device further comprises receiving means for taking in a decision signal for determining the product specification, switching signal generator means, connected to the receiving means, for producing a switching signal for changing the product specification based on the decision signal, and switching means which receives the active signal and the switching signal, and which, based on the switching signal, changes the supply of the active signal to either the first circuit section or to the second circuit section.
摘要翻译：能够改变产品规格的半导体集成电路装置。半导体集成电路装置包括集成电路部分，其包含具有第一功能的第一电路部分和具有第二功能的第二电路部分;以及主动信号发生器装置，用于产生用于激活第一电路部分或第二电路部分的有效信号。为了改变产品规格，集成电路装置还包括接收装置，用于接收用于确定产品规格的判定信号，连接到接收装置的切换信号发生器装置，用于产生用于基于决定信号和接收有源信号和切换信号的开关装置，并且基于切换信号将有源信号的供给改变为第一电路部分或第二电路部分。

6. 发明授权

US5475646A Screening circuitry for a dynamic random access memory 失效
标题翻译：动态随机存取存储器的屏蔽电路
公开(公告)号：US5475646A
公开(公告)日：1995-12-12
申请号：US342000
申请日：1994-11-16
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G11C11/407 , G01R31/317 , G11C11/401 , G11C11/403 , G11C11/406 , G11C29/00 , G11C29/06 , G11C29/14 , G11C7/00
CPC分类号： G01R31/31701
摘要： A dynamic random access memory comprising a dynamic memory section, a first screening-test pad, a second screening-test pad, and a mode-setting circuit. The dynamic memory section includes a memory-cell array having dynamic-type memory cells (MC) arranged in rows and columns, a row circuit and a column circuit, both connected to the memory-cell array, and a refresh counter for generating a refresh address signal for refreshing the dynamic-type memory cells when the dynamic memory section is set in a CBR refresh mode. The first screening-test pad receives a first external control signal for setting the dynamic memory section in an ordinary mode or a screening-test mode. The second screening-test pad receives a second external control signal for setting the dynamic memory section in the CBR refresh mode. The mode-setting circuit detects whether or not the first control signal and the second external control signal are in predetermined states, and enables the row circuit and the column circuit upon detecting that the first and second control signals are in the predetermined states, thereby to cause the refresh counter to supply the refresh address signal to the row circuit and the column circuit.
摘要翻译：一种动态随机存取存储器，包括动态存储器部分，第一筛选测试焊盘，第二屏蔽测试焊盘和模式设置电路。动态存储器部分包括具有排列成行和列的动态型存储单元（MC）的存储单元阵列，两个连接到存储单元阵列的行电路和列电路以及用于产生刷新的刷新计数器用于在动态存储器部分被设置为CBR刷新模式时刷新动态型存储器单元的地址信号。第一筛选测试垫接收用于在普通模式或筛选测试模式下设置动态存储器部分的第一外部控制信号。第二筛选测试垫接收用于将动态存储器部分设置在CBR刷新模式中的第二外部控制信号。模式设定电路检测第一控制信号和第二外部控制信号是否处于预定状态，并且在检测到第一和第二控制信号处于预定状态时使能行电路和列电路，从而使刷新计数器向行电路和列电路提供刷新地址信号。

7. 发明授权

US5272672A Semiconductor memory device having redundant circuit 失效
标题翻译：半导体存储器件具有冗余电路
公开(公告)号：US5272672A
公开(公告)日：1993-12-21
申请号：US748518
申请日：1991-08-22
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/781
摘要： An output of a column redundant circuit is supplied to one spare column selection line. The spare column selection line is provided to select the spare column line. The column redundant circuit includes four spare column decoders of the same number as that of the memory cell arrays which can be selected by the column selection line supplied with an output of a partial column decoder, and an OR gate for deriving the logical sum of outputs of the four spare column decoders and supplying the same to the spare column selection line. An output of the OR gate is supplied to a logic circuit together with an output of the partial column decoder.

8. 发明授权

US6141288A Semiconductor memory device allowing change of refresh mode and address switching method therewith 失效
标题翻译：允许更改刷新模式和地址切换方法的半导体存储器件
公开(公告)号：US6141288A
公开(公告)日：2000-10-31
申请号：US314028
申请日：1999-05-19
申请人： Kenji Numata , Masaki Ogihara
发明人： Kenji Numata , Masaki Ogihara
IPC分类号： G11C11/406 , G11C5/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/44 , G11C29/50 , G11C29/56 , H01L27/10 , G11C8/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C29/028 , G11C29/44 , G11C29/50 , G11C29/50016 , G11C5/00 , G11C5/06 , G11C7/1018 , G11C11/401
摘要： A semiconductor integrated circuit device is described. The semiconductor device includes a switching signal generator having an output terminal which outputs a switching signal to change refresh modes. The semiconductor device also includes a first address buffer having an output terminal which outputs a first address signal, a second address buffer having an output terminal which outputs a second signal, a decoder having a first input terminal which receives the first address signal and having a second input terminal, a sense amplifier controller having an input terminal, and a switch having a first input terminal which receives the switching signal, a second input terminal which receives the second address signal, a first output terminal which outputs the second address signal to the second input terminal of the decoder and a second output terminal which outputs the second address signal to the input terminal of the sense amplifier controller, the switch being controlled by the switching signal.
摘要翻译：描述半导体集成电路器件。半导体器件包括具有输出端子的开关信号发生器，该输出端子输出切换信号以改变刷新模式。半导体器件还包括具有输出第一地址信号的输出端的第一地址缓冲器，具有输出第二信号的输出端的第二地址缓冲器，具有接收第一地址信号并具有第一地址信号的第一输入端的解码器第二输入端，具有输入端的读出放大器控制器和具有接收切换信号的第一输入端的开关，接收第二地址信号的第二输入端，向第二输入端输出第二地址信号的第一输出端，所述解码器的第二输入端子和将所述第二地址信号输出到所述读出放大器控制器的输入端的第二输出端子，所述开关由所述开关信号控制。

9. 发明授权

US5812481A Semiconductor integrated circuit device allowing change of product specification and chip screening method therewith 失效
标题翻译：半导体集成电路器件允许改变产品规格和芯片筛选方法
公开(公告)号：US5812481A
公开(公告)日：1998-09-22
申请号：US683780
申请日：1996-07-16
申请人： Kenji Numata , Masaki Ogihara
发明人： Kenji Numata , Masaki Ogihara
IPC分类号： G11C11/406 , G11C5/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/44 , G11C29/50 , G11C29/56 , H01L27/10 , G11C8/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C29/028 , G11C29/44 , G11C29/50 , G11C29/50016 , G11C5/00 , G11C5/06 , G11C7/1018 , G11C11/401
摘要： A semiconductor memory device includes a buffer for outputting an address signal and a decoding circuit having an input for receiving the address signal. A switch electrically connects the buffer to the input of the decoding circuit if a refresh mode specifying signal specifies a first data refresh mode, and electrically disconnects the buffer from the input of the decoding circuit if the refresh mode specifying signal specifies a second data refresh mode different from the first data refresh mode. An activating/deactivating circuit activates the input of the decoding circuit if the refresh mode specifying signal specifies the first data refresh mode and deactivates the input of the decoding circuit if the refresh mode specifying signal specifies the second data refresh mode.
摘要翻译：半导体存储器件包括用于输出地址信号的缓冲器和具有用于接收地址信号的输入的解码电路。如果刷新模式指定信号指定第一数据刷新模式，则开关将缓冲器电连接到解码电路的输入，并且如果刷新模式指定信号指定第二数据刷新模式，则将缓冲器与解码电路的输入电断开与第一个数据刷新模式不同。如果刷新模式指定信号指定第一数据刷新模式，则激活/去激活电路激活解码电路的输入，并且如果刷新模式指定信号指定第二数据刷新模式，则解除电路的输入。

10. 发明授权

US5619162A Dram using word line potential circuit control 失效
标题翻译： Dram使用字线电位电路控制
公开(公告)号：US5619162A
公开(公告)日：1997-04-08
申请号：US658572
申请日：1996-06-05
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G11C11/407 , G11C8/08 , G11C11/4074 , G11C11/408 , G05F3/16 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4074 , G11C11/4085 , G11C11/4087
摘要： Memory cells including at least one memory cell having an n-channel MOS transistor and an n-channel MOS capacitor. A word line is connected to the memory cells. A word line drive circuit for driving the word line includes a p-channel MOS for transferring a potential to the word line. The word line drive circuit is controlled by a output from a word line potential control circuit. The word line potential control circuit applies a power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are not selected, and the word line potential control circuit applies a potential higher than a potential obtained by adding a threshold voltage of the n-channel MOS transistor to the power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are selected.
摘要翻译：存储单元包括至少一个具有n沟道MOS晶体管和n沟道MOS电容器的存储单元。字线连接到存储单元。用于驱动字线的字线驱动电路包括用于将电位传送到字线的p沟道MOS。字线驱动电路由字线电位控制电路的输出控制。当没有选择存储单元时，字线电位控制电路通过字线驱动电路中的p沟道MOS晶体管的电流路径向字线施加电源电位，并且字线电位控制电路施加电位高于通过在选择存储单元时通过字线驱动电路中的p沟道MOS晶体管的电流路径将n沟道MOS晶体管的阈值电压加到字线而获得的电位。

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