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1. 发明授权

US5410715A Interrupt controller with selectable interrupt nesting function 失效
标题翻译：具有可选中断嵌套功能的中断控制器
公开(公告)号：US5410715A
公开(公告)日：1995-04-25
申请号：US8387
申请日：1993-01-25
申请人： Satomi Ishimoto , Osamu Matsushima , Masaki Nasu , Masahiro Nomura
发明人： Satomi Ishimoto , Osamu Matsushima , Masaki Nasu , Masahiro Nomura
IPC分类号： G06F13/26
CPC分类号： G06F13/26
摘要： An interrupt controller comprises a circuit for holding information obtained by designating one priority selected from a plurality of priorities for each of a plurality of interrupt requests, and a flag for indicating whether or not a nesting is allowed for an interrupt request having at least one predetermined priority of the plurality of priorities. On the basis of the priority information held in the circuit and information held in the flag, a controller operates so that when an interrupt request is generated in the course of execution of an interrupt processing having the predetermined priority, if the flag is in a first condition, the controller acknowledges the generated interrupt request only when the priority of the generated interrupt request is higher than the predetermined priority, and if the flag is in a second condition, the controller acknowledges the generated interrupt request not only when the priority of the generated interrupt request is higher than the predetermined priority, but also when the priority of the generated interrupt request is the same as the predetermined priority.
摘要翻译：中断控制器包括一个电路，用于保存通过指定从多个中断请求中的每一个的多个优先级中选择的一个优先级获得的信息，以及用于指示是否允许具有至少一个预定的中断请求的中断请求的嵌套的标志优先考虑多项优先事项。基于保持在电路中的优先级信息和保持在标志中的信息，控制器操作，使得当在执行具有预定优先级的中断处理的过程中产生中断请求时，如果该标志位于第一条件是，只有当所产生的中断请求的优先级高于预定优先级时，控制器才确认产生的中断请求，并且如果标志处于第二状态，则控制器不仅在生成的中断请求的优先级中断请求高于预定优先级，而且当所产生的中断请求的优先级与预定优先级相同时。

2. 发明授权

US5159688A Information processor performing interrupt operation in two modes 失效
标题翻译：信息处理器在两种模式下执行中断操作
公开(公告)号：US5159688A
公开(公告)日：1992-10-27
申请号：US691284
申请日：1991-04-25
申请人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
发明人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
IPC分类号： G06F13/32
CPC分类号： G06F13/32
摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

3. 发明授权

US5163150A Information processor performing interrupt operation without saving contents of program counter 失效
标题翻译：信息处理器执行中断操作，而不保存程序计数器的内容
公开(公告)号：US5163150A
公开(公告)日：1992-11-10
申请号：US691297
申请日：1991-04-25
申请人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
发明人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
IPC分类号： G06F13/32
CPC分类号： G06F13/32
摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs and interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.
摘要翻译：信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。当处理器根据来自外围设备的请求执行和中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新启动由中断到堆栈存储器的程序执行所必需的信息的堆栈操作。虽然处理器可以在没有堆栈操作的情况下响应于第二模式信号执行中断操作，从而可以提供具有较少开销的改进的处理器。

4. 发明授权

US5036458A Information processor executing interruption program without saving contents of program counter 失效
标题翻译：信息处理器执行中断程序，而不保存程序计数器的内容
公开(公告)号：US5036458A
公开(公告)日：1991-07-30
申请号：US287622
申请日：1988-12-20
申请人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
发明人： Osamu Matsushima , Yukio Maehashi , Shigetatsu Katori , Masahiro Nomura , Hiroko Shinohara , Kohichi Kariya , Mitsue Abe
IPC分类号： G06F13/32
CPC分类号： G06F13/32
摘要： An information processor has at least one interface unit by which the processor is coupled to peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart execution of a program which is stopped by the interruption in a stack memory is performed before the start of the interruption operation. The processor can perform the interruption operation in response to the second mode signal without the stack operation, providing an improved processor with less overhead. The two interruption mode technique is described in a number of applications, including D/A conversion, serial data transmission and reception, and operation of computer peripheral devices.
摘要翻译：信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。当处理器根据来自外围设备的请求执行中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新执行由堆栈存储器中的中断而停止的程序所需的信息的堆栈操作。处理器可以在不进行堆栈操作的情况下响应于第二模式信号执行中断操作，从而提供具有较少开销的改进的处理器。在多种应用中描述了两种中断模式技术，包括D / A转换，串行数据传输和接收以及计算机外围设备的操作。

5. 发明申请

US20130165482A1 PEST CONTROL AGENT 有权
标题翻译：虫控制剂
公开(公告)号：US20130165482A1
公开(公告)日：2013-06-27
申请号：US13814753
申请日：2011-08-26
申请人： Shinzo Kagabu , Masaaki Mitomi , Shigeki Kitsuda , Ryo Horikoshi , Masahiro Nomura , Yasumichi Onozaki
发明人： Shinzo Kagabu , Masaaki Mitomi , Shigeki Kitsuda , Ryo Horikoshi , Masahiro Nomura , Yasumichi Onozaki
IPC分类号： C07D211/98 , A01N43/40
CPC分类号： A01N43/40 , A01N37/18 , A01N43/50 , A01N43/54 , A01N43/58 , A01N43/78 , A01N47/02 , A01N47/12 , A01N47/40 , A01N57/32 , C07C233/05 , C07C233/12 , C07C261/04 , C07C271/12 , C07C311/09 , C07D211/98 , C07D213/36 , C07D213/40 , C07D213/42 , C07D213/61 , C07D213/75 , C07D237/08 , C07D277/32 , C07D333/20 , C07D401/06 , C07D401/12 , C07D405/12 , C07D417/12 , C07F9/58
摘要： Specific amine derivatives have been found to possess excellent activities as pest control agents.
摘要翻译：已发现特定的胺衍生物作为害虫控制剂具有优良的活性。

6. 发明申请

US20110263608A1 16-KETO ASPERGILLIMIDES AND HARMFUL ORGANISM CONTROL AGENT COMPRISING THE SAME AS ACTIVE INGREDIENT 审中-公开
标题翻译： 16-KETO ASPERGILLIMIDES和包含其中有效成分的有机有机体控制剂
公开(公告)号：US20110263608A1
公开(公告)日：2011-10-27
申请号：US13140625
申请日：2009-12-21
申请人： Kenichi Kurihara , Ryo Horikoshi , Masahiro Nomura , Satoshi Nakamura , Mizuki Hayashimoto , Mariko Tsuchida , Nobuto Minowa
发明人： Kenichi Kurihara , Ryo Horikoshi , Masahiro Nomura , Satoshi Nakamura , Mizuki Hayashimoto , Mariko Tsuchida , Nobuto Minowa
IPC分类号： A61K31/4995 , A01P7/04 , A61P33/14 , C07D487/22 , A01N43/58
CPC分类号： C07D471/22 , A01N43/90 , C07D491/22
摘要： Disclosed is a composition for use in controlling ectoparasites, comprising as an active ingredient at least one of compounds represented by formula (I) or (III) or salts thereof. The present invention provides a composition for use in controlling ectoparasites that has excellent ectoparasite control effect and is highly safe.
摘要翻译：公开了用于控制外寄生物的组合物，其包含作为活性成分的至少一种由式（I）或（III）表示的化合物或其盐。本发明提供一种用于控制具有优异的外寄生物控制效果并且高度安全的外寄生虫的组合物。

7. 发明申请

US20110263520A1 COMPOSITION FOR USE IN CONTROLLING HARMFUL ORGANISMS THAT CONTAINS 16-KETO ASPERGILLIMIDE 审中-公开
标题翻译：用于控制含有16-KETO ASPERGILLIMIDE的有害有机体的组合物
公开(公告)号：US20110263520A1
公开(公告)日：2011-10-27
申请号：US13140582
申请日：2009-12-21
申请人： Ryo Horikoshi , Masahiro Nomura , Satoshi Nakamura , Mizuki Hayashimoto , Mariko Tsuchida , Kazuhiko Oyama , Masaaki Mitomi
发明人： Ryo Horikoshi , Masahiro Nomura , Satoshi Nakamura , Mizuki Hayashimoto , Mariko Tsuchida , Kazuhiko Oyama , Masaaki Mitomi
IPC分类号： A61K31/7048 , A61K31/4985 , A01P1/00 , A01P3/00 , A01P7/04 , A61P33/00 , A01N43/90 , A61K31/5395
CPC分类号： A01N43/90 , A01N43/40 , A01N43/80 , A01N47/02 , A01N47/40 , A01N51/00 , A01N2300/00
摘要： Disclosed is a composition for use in controlling harmful organisms, comprising as active ingredients at least one of 16-keto aspergillimide, its enantiomers, their mixture, or their acid addition salts and at least one of other harmful organism control agents. The present invention provides a composition for use in controlling harmful organisms that has excellent insecticidal activity or penetrative transferable insecticidal activity against a wide range of harmful organisms, particularly agricultural and horticultural insect pests.
摘要翻译：公开了一种用于控制有害生物体的组合物，其包含16-酮基曲霉亚胺，其对映异构体，其混合物或其酸加成盐和至少一种其它有害生物体控制剂中的至少一种作为活性成分。本发明提供了一种用于控制对广泛的有害生物，特别是农业和园艺害虫具有优异的杀虫活性或渗透性可转移杀虫活性的有害生物的组合物。

8. 发明授权

US07659772B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07659772B2
公开(公告)日：2010-02-09
申请号：US11813502
申请日：2006-01-06
申请人： Masahiro Nomura , Koichi Takeda
发明人： Masahiro Nomura , Koichi Takeda
IPC分类号： G05F1/10
CPC分类号： H03K19/0008
摘要： A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.
摘要翻译：一种半导体集成电路器件，包括：用于观察开关电流的开关电流观察器; 用于观察泄漏电流的漏电流观测器; 将开关电流和漏电流进行比较的比较器; 用于控制衬底偏置电压以使开关电流和漏电流的比率恒定的阈值电压控制器; 用于观察延迟量的延迟观察器; 以及用于控制电源电压以便将延迟量保持在预定范围内的电源电压控制器。在半导体集成电路器件中，通过控制阈值电压来实现能够最小化操作功率的处理，以使给定时钟频率下的开关电流和漏电流的比率恒定，并将电源电压控制为保证运行速度。

9. 发明申请

US20090274575A1 PRECISION ALLOY 审中-公开
标题翻译：精密合金
公开(公告)号：US20090274575A1
公开(公告)日：2009-11-05
申请号：US12439940
申请日：2007-09-20
申请人： Masahiro Nomura
发明人： Masahiro Nomura
IPC分类号： C22C18/04 , C22C30/02
CPC分类号： C22C18/04 , C22C30/02 , C22C30/06 , C22F1/00 , C22F1/10
摘要： A precision alloy for die-casting contains aluminum, silicon and zinc, wherein on the basis of the overall mass, the content of aluminum is 40% by mass or more and 45% by mass or less, and the content of silicon is 2% by mass or more and 8% by mass or less. Also other solving means will be described.
摘要翻译：用于压铸的精密合金包含铝，硅和锌，其中基于总质量，铝的含量为40质量％以上且45质量％以下，硅的含量为2质量％以上且8质量％以下。还将描述其他解决方案。

10. 发明申请

US20090014795A1 Substrate for field effect transistor, field effect transistor and method for production thereof 审中-公开
标题翻译：场效应晶体管用基板，场效应晶体管及其制造方法
公开(公告)号：US20090014795A1
公开(公告)日：2009-01-15
申请号：US11658564
申请日：2005-07-14
申请人： Risho Koh , Katsuhiko Tanaka , Shigeharu Yamagami , Koichi Terashima , Hitoshi Wakabayashi , Kiyoshi Takeuchi , Masayasu Tanaka , Masahiro Nomura , Koichi Takeda
发明人： Risho Koh , Katsuhiko Tanaka , Shigeharu Yamagami , Koichi Terashima , Hitoshi Wakabayashi , Kiyoshi Takeuchi , Masayasu Tanaka , Masahiro Nomura , Koichi Takeda
IPC分类号： H01L29/786 , H01L27/12 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A π gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.
摘要翻译：提供了一种具有减小的截止电流和寄生电容的变化的p型门FinFET结构及其制造方法。改善了元件的结构，使得能够更强烈地显示出截止电流的能力。一种场效应晶体管，其中第一绝缘膜和半导体区域设置成相对于基底的平坦表面向上突出，所述场效应晶体管具有栅极电极，栅极绝缘膜和源极/漏极区域并且至少在所述半导体区域的侧表面上形成沟道，其中所述第一绝缘膜设置在由蚀刻速率低于所述第一绝缘膜的最下层的蚀刻速率的材料构成的蚀刻停止层上用于在预定条件下蚀刻。

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