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1. 发明授权

US07620075B2 Serial communication system with baud rate generator 有权
标题翻译：具有波特率发生器的串行通信系统
公开(公告)号：US07620075B2
公开(公告)日：2009-11-17
申请号：US11806006
申请日：2007-05-29
申请人： Satomi Ishimoto
发明人： Satomi Ishimoto
IPC分类号： H04J1/16 , H04J3/06
CPC分类号： H04L25/40 , H04L7/0331 , H04L7/046 , H04L25/05
摘要： A baud rate generator includes a first counter, a timer and a baud rate correcting circuit. The first counter is configured to count bits of an inputted serial data. The timer is configured to measure a time for which the first counter counts a predetermined number of bits based on a reference clock signal. The baud rate correcting circuit is configured to output a baud rate correction value based on the measurement time by the timer such that a baud rate in a serial communication is corrected based on the baud rate correction value.
摘要翻译：波特率发生器包括第一计数器，定时器和波特率校正电路。第一计数器被配置为对输入的串行数据的位进行计数。定时器被配置为基于参考时钟信号来测量第一计数器对预定位数进行计数的时间。波特率校正电路被配置为基于定时器的测量时间输出波特率校正值，使得基于波特率校正值校正串行通信中的波特率。

2. 发明授权

US06460091B1 Address decoding circuit and method for identifying individual addresses and selecting a desired one of a plurality of peripheral macros 失效
标题翻译：地址解码电路和方法，用于识别各个地址并选择多个外围宏中所需的一个
公开(公告)号：US06460091B1
公开(公告)日：2002-10-01
申请号：US09291221
申请日：1999-04-13
申请人： Satomi Ishimoto
发明人： Satomi Ishimoto
IPC分类号： G06F300
CPC分类号： G11C29/18
摘要： There is provided an address decoding circuit including (a) a first address decoder for practical use for decoding an address which is particular to an individual object, (b) a second address decoder for test use for decoding a constant address regardless of objects, and (c) a logic circuit receiving a selection signal and switching from decoding result transmitted thereto from the first address decoder to decoding result transmitted thereto from the second address decoder, and vice versa in accordance with the selection signal. The address decoding circuit selects decoding result of an address used for a test, which is particular to peripheral macros, in a test mode in accordance with the selection signal. Hence, when peripheral macros are mounted on different chips, it would be possible to use a common vector, even if an address for practical use is changed. This ensures reduction in steps of re-constructing test vector.
摘要翻译：提供了一种地址解码电路，包括：（a）实际使用的第一地址解码器，用于对特定于单个对象的地址进行解码;（b）第二地址解码器，用于解码恒定地址而不管对象;以及（c）逻辑电路，接收选择信号，并将从第一地址解码器传输的解码结果切换到从第二地址解码器传输到其的解码结果，反之亦然。地址解码电路根据选择信号在测试模式中选择用于测试的地址的解码结果，这是特定于外设宏的。因此，当外围宏安装在不同的芯片上时，即使改变实际使用的地址，也可以使用公共矢量。这确保了重新构建测试向量的步骤的减少。

3. 发明申请

US20070291887A1 Serial communication system with baud rate generator 有权
标题翻译：具有波特率发生器的串行通信系统
公开(公告)号：US20070291887A1
公开(公告)日：2007-12-20
申请号：US11806006
申请日：2007-05-29
申请人： Satomi Ishimoto
发明人： Satomi Ishimoto
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L25/40 , H04L7/0331 , H04L7/046 , H04L25/05
摘要： A baud rate generator includes a first counter, a timer and a baud rate correcting circuit. The first counter is configured to count bits of an inputted serial data. The timer is configured to measure a time for which the first counter counts a predetermined number of bits based on a reference clock signal. The baud rate correcting circuit is configured to output a baud rate correction value based on the measurement time by the timer such that a baud rate in a serial communication is corrected based on the baud rate correction value.
摘要翻译：波特率发生器包括第一计数器，定时器和波特率校正电路。第一计数器被配置为对输入的串行数据的位进行计数。定时器被配置为基于参考时钟信号来测量第一计数器对预定位数进行计数的时间。波特率校正电路被配置为基于定时器的测量时间输出波特率校正值，使得基于波特率校正值校正串行通信中的波特率。

4. 发明授权

US4996639A Data processor including an A/D converter for converting a plurality of analog input channels into digital data 失效
标题翻译：数据处理器包括用于将多个模拟输入通道转换为数字数据的A / D转换器
公开(公告)号：US4996639A
公开(公告)日：1991-02-26
申请号：US276970
申请日：1988-11-28
申请人： Satomi Ishimoto , Osamu Matsushima , Hajime Sakuma
发明人： Satomi Ishimoto , Osamu Matsushima , Hajime Sakuma
IPC分类号： G06F3/05
CPC分类号： G06F3/05
摘要： A data processor includes a CPU and an A/D converter for converting one of several analog inputs into digital data. A data memory stores data designating analog inputs to be converted. A circuit, responsive to an A/D conversion completion signal from the A/D converter, supplies a macro service operation request to the CPU, which interrupts the CPU without having to save the contents of a CPU program counter and a CPU status register. Upon completion of the A/D conversion, the converted digital data are stored in a predetermined location, and CPU execution resumes.

5. 发明授权

US5479566A Microcomputer internally having fuzzy inference exclusive-instructions 失效
标题翻译：微机内部具有模糊推理专用指令
公开(公告)号：US5479566A
公开(公告)日：1995-12-26
申请号：US163055
申请日：1993-12-06
申请人： Satomi Ishimoto , Hajime Sakuma
发明人： Satomi Ishimoto , Hajime Sakuma
IPC分类号： G06F9/44 , G06F9/30 , G06F9/302 , G06F9/32 , G06N7/02 , G06N7/04 , G06F15/18
CPC分类号： G06F9/3001 , G06F9/30021 , G06F9/325 , G06N7/04 , Y10S706/90
摘要： In a microcomputer including a processor, a data memory and a controller for controlling the processor and the data memory, the data memory includes a adaptivity degree data group indicative of the adaptivity degree to the fuzzy set, and an area for storing the result of processing. The processor includes an adaptivity degree data pointer, a result store area pointer, a conformity degree data storing register, and a processing number count register. The microcomputer internally includes a fuzzy inference exclusive-instruction, which causes to compare data in the conformity degree data storing register with data designated by the adaptivity degree data pointer, so as to select a smaller one, and compare the selected dam with data designated by the result store area pointer, so as to store a large one at the area for storing the result of processing, designated by the the result store area pointer. The above processings are repealed the number of processing in the processing number count register, while updating the result store area pointer and the adaptivity degree data group pointer.
摘要翻译：在包括处理器，数据存储器和用于控制处理器和数据存储器的控制器的微型计算机中，数据存储器包括表示对模糊集的自适应度的自适应度数据组和用于存储处理结果的区域。处理器包括自适应度数据指针，结果存储区域指针，一致度数据存储寄存器和处理数量计数寄存器。微型计算机内部包括模糊推理专用指令，其使比较数据存储寄存器中的数据与自适应度数据指针指定的数据进行比较，以便选择较小的数据，并将选定的大坝与由结果存储区指针，以便在用于存储由结果存储区指针指定的处理结果的区域处存储大数据。在更新结果存储区域指针和自适应度数据组指针的同时，将处理数量计数寄存器中的处理次数废除上述处理。

6. 发明授权

US5410715A Interrupt controller with selectable interrupt nesting function 失效
标题翻译：具有可选中断嵌套功能的中断控制器
公开(公告)号：US5410715A
公开(公告)日：1995-04-25
申请号：US8387
申请日：1993-01-25
申请人： Satomi Ishimoto , Osamu Matsushima , Masaki Nasu , Masahiro Nomura
发明人： Satomi Ishimoto , Osamu Matsushima , Masaki Nasu , Masahiro Nomura
IPC分类号： G06F13/26
CPC分类号： G06F13/26
摘要： An interrupt controller comprises a circuit for holding information obtained by designating one priority selected from a plurality of priorities for each of a plurality of interrupt requests, and a flag for indicating whether or not a nesting is allowed for an interrupt request having at least one predetermined priority of the plurality of priorities. On the basis of the priority information held in the circuit and information held in the flag, a controller operates so that when an interrupt request is generated in the course of execution of an interrupt processing having the predetermined priority, if the flag is in a first condition, the controller acknowledges the generated interrupt request only when the priority of the generated interrupt request is higher than the predetermined priority, and if the flag is in a second condition, the controller acknowledges the generated interrupt request not only when the priority of the generated interrupt request is higher than the predetermined priority, but also when the priority of the generated interrupt request is the same as the predetermined priority.
摘要翻译：中断控制器包括一个电路，用于保存通过指定从多个中断请求中的每一个的多个优先级中选择的一个优先级获得的信息，以及用于指示是否允许具有至少一个预定的中断请求的中断请求的嵌套的标志优先考虑多项优先事项。基于保持在电路中的优先级信息和保持在标志中的信息，控制器操作，使得当在执行具有预定优先级的中断处理的过程中产生中断请求时，如果该标志位于第一条件是，只有当所产生的中断请求的优先级高于预定优先级时，控制器才确认产生的中断请求，并且如果标志处于第二状态，则控制器不仅在生成的中断请求的优先级中断请求高于预定优先级，而且当所产生的中断请求的优先级与预定优先级相同时。

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