专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07041516B2 Multi chip module assembly 有权
标题翻译：多芯片模块组装
公开(公告)号：US07041516B2
公开(公告)日：2006-05-09
申请号：US10268361
申请日：2002-10-10
申请人： Sarathy Rajagopalan , Kishor Desai , John P. McCormick , Maniam Alagaratnam
发明人： Sarathy Rajagopalan , Kishor Desai , John P. McCormick , Maniam Alagaratnam
IPC分类号： H01L21/50 , G01R31/26
CPC分类号： H01L25/50 , H01L22/20 , H01L23/5385 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/014 , H01L2924/15311 , H01L2924/16152 , H01L2224/0401
摘要： A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.
摘要翻译：一种将至少第一集成电路和第二集成电路组装到多芯片模块中的方法。第一集成电路被附接并电连接到第一基板以形成第一组件，其被测试以确保其正常工作。第二集成电路被连接并电连接到第二基板以形成第二组件，其也被测试以确保其正常工作。第一组件被附接并电连接到第二组件以形成多芯片模块。

2. 发明授权

US06586825B1 Dual chip in package with a wire bonded die mounted to a substrate 有权
标题翻译：双芯片封装，带有焊线芯片，安装在基板上
公开(公告)号：US06586825B1
公开(公告)日：2003-07-01
申请号：US09843443
申请日：2001-04-26
申请人： Sarathy Rajagopalan , Kishor Desai , Maniam Alagaratnam
发明人： Sarathy Rajagopalan , Kishor Desai , Maniam Alagaratnam
IPC分类号： H05K116
CPC分类号： H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06572 , H01L2225/06575 , H01L2924/00014 , H01L2924/00012
摘要： A package comprises a top die and a bottom die. The top die has top and bottom surfaces while the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top surface, such that the bottom surface of the bottom die faces the top surface of the substrate. The bottom surface of the top die is separated from the top surface of the bottom die by an interposer, which creates a space between the exterior regions of the top surface of the bottom die and the bottom surface of the top die. Each of a plurality of wires, which are electrically connected to the bottom die, runs through this space (i.e. runs between the top surface of the bottom die and the bottom surface of the top die), thereby permitting (if desired) the top die to be at least as large as the bottom die.
摘要翻译：包装包括顶模和底模。顶部模具具有顶部和底部表面，而底部模具具有顶部和底部表面。底模安装在具有顶表面的基底上，使得底模的底表面面向基底的顶表面。顶部模具的底表面通过插入件与底模的顶表面分离，其在底模的顶表面的外部区域和顶模的底表面之间产生空间。电连接到底模的多根导线中的每一根穿过该空间（即，在底模的顶表面和顶模的底表面之间延伸），从而允许（如果需要）顶模至少与底部模具一样大。

3. 发明授权

US06777314B2 Method of forming electrolytic contact pads including layers of copper, nickel, and gold 有权
标题翻译：形成包括铜，镍和金层的电解接触焊盘的方法
公开(公告)号：US06777314B2
公开(公告)日：2004-08-17
申请号：US10211914
申请日：2002-08-05
申请人： Kishor Desai , John P. McCormick , Maniam Alagaratnam
发明人： Kishor Desai , John P. McCormick , Maniam Alagaratnam
IPC分类号： H01L21326
CPC分类号： H05K3/062 , H01L21/2885 , H01L21/4853 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/13099 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K3/108 , H05K3/243 , H01L2224/05644 , H01L2924/00014 , H01L2224/05147 , H01L2224/05155
摘要： A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is formed in a substantially contiguous sheet across the surface of the substrate. A non electrically conductive masking layer is applied to the first layer, where the masking layer leaves exposed first portions of the first layer and covers second portions of the first layer. The substrate is immersed in a first electrolytic plating bath, and a first electrical potential is applied between the first layer and the first electrolytic plating bath, thereby causing the formation of a second layer of a second electrically conductive material on the exposed first portions of the first layer. The substrate is immersed in a second electrolytic plating bath, and a second electrical potential is applied between the first layer and the second electrolytic plating bath, thereby causing the formation of a third layer of a third electrically conductive material on the second layer. The masking layer is removed from the substrate to expose the second portions of the first layer, and the exposed second portions of the first layer are removed to form discrete contact pads from the first portions of the first layer and the overlying second layer and third layer.
摘要翻译：在基板的表面上形成电接触的方法。在衬底的表面上形成第一导电材料第一层，其中第一层在基片的表面上形成在基本连续的片材中。将非导电掩蔽层施加到第一层，其中掩蔽层离开第一层的暴露的第一部分并覆盖第一层的第二部分。将衬底浸入第一电解电镀浴中，并且在第一层和第一电解镀浴之间施加第一电位，由此在第二层导电材料的暴露的第一部分上形成第二导电材料层第一层将衬底浸入第二电解镀浴中，并且在第一层和第二电解镀浴之间施加第二电位，从而在第二层上形成第三层第三导电材料层。从衬底去除掩模层以暴露第一层的第二部分，并且去除第一层的暴露的第二部分以从第一层的第一部分和上覆的第二层和第三层形成分立的接触焊盘。

4. 发明申请

US20050224955A1 Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package 有权
标题翻译：用于在半导体封装中建立管芯和散热器之间的改善的热连通的方法和装置
公开(公告)号：US20050224955A1
公开(公告)日：2005-10-13
申请号：US10820494
申请日：2004-04-07
申请人： Kishor Desai , Maniam Alagaratnam
发明人： Kishor Desai , Maniam Alagaratnam
IPC分类号： H01L21/48 , H01L23/31 , H01L23/34 , H01L23/36 , H01L23/433
CPC分类号： H01L23/3128 , H01L23/36 , H01L23/433 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16195 , H01L2924/00
摘要： A semiconductor package comprising a packaging substrate, a semiconductor die mounted with the substrate, a heatspreader, and a multi-layer heat transfer element arranged between the semiconductor die and the heat spreader to enable thermal communication between the die and the heat spreader is disclosed. The multi-layer heat transfer element includes a core spacer element sandwiched between a first layer of thermally conductive reflowable material and a second layer of thermally conductive reflowable material. Also disclosed are methods for forming such semiconductor packages and for forming multilayer heat transfer elements.
摘要翻译：公开了一种半导体封装，其包括封装衬底，安装有衬底的半导体管芯，散热器和布置在半导体管芯和散热器之间的多层传热元件，以实现管芯和散热器之间的热连通。多层传热元件包括夹在第一层导热可回流材料和第二层导热可回流材料之间的芯间隔件。还公开了形成这种半导体封装和形成多层传热元件的方法。

5. 发明授权

US5923047A Semiconductor die having sacrificial bond pads for die test 失效
标题翻译：具有用于模具测试的牺牲接合焊盘的半导体管芯
公开(公告)号：US5923047A
公开(公告)日：1999-07-13
申请号：US837618
申请日：1997-04-21
申请人： Chok J. Chia , Qwai H. Low , Maniam Alagaratnam
发明人： Chok J. Chia , Qwai H. Low , Maniam Alagaratnam
IPC分类号： G01R31/28 , H01L21/301 , H01L23/485 , H01L23/58 , H01L21/60 , H01L21/66
CPC分类号： H01L24/06 , H01L22/32 , G01R31/2884 , H01L2224/05553 , H01L2924/01013 , H01L2924/01033 , H01L2924/14
摘要： The testing of integrated circuits in a plurality of dice arranged in rows and columns in a semiconductor wafer is facilitated by effectively increasing the pitch between adjacent input/output bonding pads on each die by providing a plurality of test pads in scribing space between adjacent die. Alternate test pads are connected with alternate bonding pads on adjacent die, thereby effectively increasing the pitch of adjacent die for testing. After the integrated circuits are tested and defective circuits are marked, the wafer is scribed in the scribe space and broken to recover the individual die or integrated circuit chips.
摘要翻译：通过在相邻的管芯之间的刻划空间中提供多个测试焊盘，通过有效地增加每个管芯上相邻的输入/输出焊盘之间的间距，有助于半导体晶片中以行和列布置的多个管芯中的集成电路的测试。替代的测试焊盘与相邻裸片上的替代焊盘相连，从而有效地增加相邻裸片的间距以进行测试。在对集成电路进行测试并且标记故障电路之后，在刻划空间刻划晶片并断开晶片以恢复单独的芯片或集成电路芯片。

6. 发明授权

US5927505A Overmolded package body on a substrate 失效
标题翻译：包覆成型的包装体在基材上
公开(公告)号：US5927505A
公开(公告)日：1999-07-27
申请号：US920430
申请日：1997-08-29
申请人： Chok J. Chia , Seng-Sooi Lim , Maniam Alagaratnam
发明人： Chok J. Chia , Seng-Sooi Lim , Maniam Alagaratnam
IPC分类号： B29C45/14 , H01L21/56 , H01L23/31 , B65D73/02 , H01L23/04
CPC分类号： B29C45/14418 , B29C45/14655 , H01L21/565 , H01L23/3121 , B29C2045/14934 , B29C70/72 , B29C70/78 , H01L2924/0002
摘要： Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.
摘要翻译：具有宽范围厚度并且旨在用塑料封装体包覆成型的基板容纳在共同的模具中。衬底的顶表面设置有坝结构，其可以在衬底上形成为附加层，并且其优选地为正方形环的形式。槽（通道）被加工（例如通过路由）到坝结构的表面中。具有用于形成封装主体的空腔的顶部模具半部在空腔的周边处设置有密封结构。密封结构具有嵌入坝结构通道的脊。容易调节坝结构中槽的深度，以确保上模半部在基板上的均匀夹紧压力，使得液体模塑料被包含在空腔内，从而不会对衬底施加过大的压力。

7. 发明授权

US06433565B1 Test fixture for flip chip ball grid array circuits 有权
标题翻译：用于倒装芯片球栅阵列电路的测试夹具
公开(公告)号：US06433565B1
公开(公告)日：2002-08-13
申请号：US09846435
申请日：2001-05-01
申请人： Kishor V. Desai , Maniam Alagaratnam , Sunil A. Patel
发明人： Kishor V. Desai , Maniam Alagaratnam , Sunil A. Patel
IPC分类号： G01R3102
CPC分类号： G01R1/07371 , G01R1/07357
摘要： A test fixture for a ball grid array package is disclosed that includes a test ball grid array package having a plurality of coarse pitch contacts formed on a coarse pitch surface of the test ball grid array package and a plurality of wafer bumps formed on a fine pitch surface of the test ball grid array package and an interposer coupled to the plurality of wafer bumps formed on the fine pitch surface of the test ball grid array package for coupling to a plurality of wafer bumps formed on a fine pitch surface of a subject ball grid array package.
摘要翻译：公开了一种用于球栅阵列封装的测试夹具，其包括测试球栅阵列封装，其具有形成在测试球栅阵列封装的粗节距表面上的多个粗节距触点和形成在细间距上的多个晶片凸块测试球栅阵列封装的表面和耦合到形成在测试球栅阵列封装的细间距表面上的多个晶片凸块的插入件，用于耦合到形成在主体球栅格的细间距表面上的多个晶片凸块阵列包。

8. 发明授权

US5869889A Thin power tape ball grid array package 失效
标题翻译：薄电动带球栅阵列封装
公开(公告)号：US5869889A
公开(公告)日：1999-02-09
申请号：US840614
申请日：1997-04-21
申请人： Chok J. Chia , Patrick Variot , Maniam Alagaratnam
发明人： Chok J. Chia , Patrick Variot , Maniam Alagaratnam
IPC分类号： H01L23/29 , H01L21/60 , H01L23/12 , H01L23/24 , H01L23/31 , H01L23/36 , H01L23/498 , H01L23/34
CPC分类号： H01L23/36 , H01L23/24 , H01L23/4985 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181
摘要： An integrated circuit package includes a heatspreader which is formed to have a centrally disposed recessed portion between planar surfaces, and flex tape extending from the planar surfaces into the centrally disposed surface. A semiconductor chip is mounted on the centrally disposed surface between the flex tape, and wire bonds interconnect bonding pads on the chip to the metal interconnect patterns on the flex tape. Plastic molding or epoxy is then applied to encapsulate the chip and wire bonding in the centrally disposed planar surface of the heat spreader. The package is then readily mounted on a motherboard using solder balls.
摘要翻译：集成电路封装包括散热器，其形成为在平面之间具有居中设置的凹部，以及从平面延伸到中心设置表面的柔性带。半导体芯片安装在柔性带之间的中央布置的表面上，并且引线将芯片上的接合焊盘互连到柔性带上的金属互连图案。然后施加塑料模制或环氧树脂以将芯片和引线接合封装在散热器的中心设置的平坦表面中。然后使用焊球将封装容易地安装在母板上。

9. 发明授权

US06608376B1 Integrated circuit package substrate with high density routing mechanism 有权
标题翻译：具有高密度路由机制的集成电路封装基板
公开(公告)号：US06608376B1
公开(公告)日：2003-08-19
申请号：US10105863
申请日：2002-03-25
申请人： Wee Keong Liew , Aritharan Thurairajaratnam , Maniam Alagaratnam
发明人： Wee Keong Liew , Aritharan Thurairajaratnam , Maniam Alagaratnam
IPC分类号： H01L2304
CPC分类号： H05K1/114 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/49175 , H01L2224/49433 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H05K2201/09627 , H01L2924/00014 , H01L2924/00015 , H01L2924/00012
摘要： An integrated circuit package is provided that allows high density routing of signal lines. A substrate of the package may include an upper surface upon which a bonding finger resides, a lower surface upon which a solder ball resides, and a signal conductor plane on which a signal trace conductor resides a dielectrically spaced distance between the upper surface and the lower surface. A first via may extend perpendicularly from the upper surface, connecting the bonding finger to the first portion of the signal trace conductor. A second via may extend perpendicularly from the lower surface, connecting the solder ball to the second portion of the signal trace conductor. The routing of the vias and signal trace conductors may cause the signal lines to either fan into or away from the area of the integrated circuit package adapted to receive the integrated circuit.
摘要翻译：提供集成电路封装，允许信号线的高密度布线。封装的基板可以包括粘结指状物所在的上表面，焊球所在的下表面和信号导线平面，信号导线平面在上表面和下表面之间介于介电间隔的距离表面。第一通孔可以从上表面垂直延伸，将接合指连接到信号迹线导体的第一部分。第二通孔可以从下表面垂直延伸，将焊球连接到信号迹线导体的第二部分。通孔和信号迹线导体的路由可能导致信号线风扇进入或远离适合于接收集成电路的集成电路封装的区域。

10. 发明授权

US06335491B1 Interposer for semiconductor package assembly 有权
标题翻译：用于半导体封装组装的插入器
公开(公告)号：US06335491B1
公开(公告)日：2002-01-01
申请号：US09499801
申请日：2000-02-08
申请人： Maniam Alagaratnam , Kishor V. Desai , Sunil A. Patel
发明人： Maniam Alagaratnam , Kishor V. Desai , Sunil A. Patel
IPC分类号： H05K116
CPC分类号： H05K3/3436 , H01L23/49827 , H01L23/49833 , H01L2224/16225 , H01L2924/00014 , H01L2924/01078 , H01L2924/01322 , H01L2924/15311 , H01L2924/15312 , H05K3/284 , H05K2201/049 , H05K2201/10378 , H05K2201/10977 , H05K2203/041 , Y02P70/613 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/53174 , H01L2224/0401
摘要： The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.
摘要翻译：本发明描述了一种提高半导体器件的热性能的插入器。插入器可以位于基板和板之间。插入件连接到两层焊球。第一层焊球将电介质和机械连接到衬底。第二层焊球电连接和机械连接插入器到板。在一个方面，可以灵活地选择中介层的热膨胀系数（CTE），以减小由于衬底与插入件或插入件之间的热性能差异导致的两个或两个焊球层的热应变诱发应力，板。在另一方面，可以减小中介层的CTE以允许衬底的较低CTE，这反过来可以降低衬底和附接到衬底的管芯之间的焊球的热应变诱发应力。有利地，本发明的改进的热性能可以允许更大的基板，更大的管芯，较大的焊球阵列，减少的焊球间距和引脚数远远高于传统的等级，而不会影响半导体器件的可靠性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式