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1. 发明授权

US06433565B1 Test fixture for flip chip ball grid array circuits 有权
标题翻译：用于倒装芯片球栅阵列电路的测试夹具
公开(公告)号：US06433565B1
公开(公告)日：2002-08-13
申请号：US09846435
申请日：2001-05-01
申请人： Kishor V. Desai , Maniam Alagaratnam , Sunil A. Patel
发明人： Kishor V. Desai , Maniam Alagaratnam , Sunil A. Patel
IPC分类号： G01R3102
CPC分类号： G01R1/07371 , G01R1/07357
摘要： A test fixture for a ball grid array package is disclosed that includes a test ball grid array package having a plurality of coarse pitch contacts formed on a coarse pitch surface of the test ball grid array package and a plurality of wafer bumps formed on a fine pitch surface of the test ball grid array package and an interposer coupled to the plurality of wafer bumps formed on the fine pitch surface of the test ball grid array package for coupling to a plurality of wafer bumps formed on a fine pitch surface of a subject ball grid array package.
摘要翻译：公开了一种用于球栅阵列封装的测试夹具，其包括测试球栅阵列封装，其具有形成在测试球栅阵列封装的粗节距表面上的多个粗节距触点和形成在细间距上的多个晶片凸块测试球栅阵列封装的表面和耦合到形成在测试球栅阵列封装的细间距表面上的多个晶片凸块的插入件，用于耦合到形成在主体球栅格的细间距表面上的多个晶片凸块阵列包。

2. 发明授权

US06335491B1 Interposer for semiconductor package assembly 有权
标题翻译：用于半导体封装组装的插入器
公开(公告)号：US06335491B1
公开(公告)日：2002-01-01
申请号：US09499801
申请日：2000-02-08
申请人： Maniam Alagaratnam , Kishor V. Desai , Sunil A. Patel
发明人： Maniam Alagaratnam , Kishor V. Desai , Sunil A. Patel
IPC分类号： H05K116
CPC分类号： H05K3/3436 , H01L23/49827 , H01L23/49833 , H01L2224/16225 , H01L2924/00014 , H01L2924/01078 , H01L2924/01322 , H01L2924/15311 , H01L2924/15312 , H05K3/284 , H05K2201/049 , H05K2201/10378 , H05K2201/10977 , H05K2203/041 , Y02P70/613 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/53174 , H01L2224/0401
摘要： The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.
摘要翻译：本发明描述了一种提高半导体器件的热性能的插入器。插入器可以位于基板和板之间。插入件连接到两层焊球。第一层焊球将电介质和机械连接到衬底。第二层焊球电连接和机械连接插入器到板。在一个方面，可以灵活地选择中介层的热膨胀系数（CTE），以减小由于衬底与插入件或插入件之间的热性能差异导致的两个或两个焊球层的热应变诱发应力，板。在另一方面，可以减小中介层的CTE以允许衬底的较低CTE，这反过来可以降低衬底和附接到衬底的管芯之间的焊球的热应变诱发应力。有利地，本发明的改进的热性能可以允许更大的基板，更大的管芯，较大的焊球阵列，减少的焊球间距和引脚数远远高于传统的等级，而不会影响半导体器件的可靠性。

3. 发明授权

US06618938B1 Interposer for semiconductor package assembly 有权
公开(公告)号：US06618938B1
公开(公告)日：2003-09-16
申请号：US09974157
申请日：2001-10-09
申请人： Maniam Alagaratnam , Kishor V. Desai , Sunil A. Patel
发明人： Maniam Alagaratnam , Kishor V. Desai , Sunil A. Patel
IPC分类号： H05K334
CPC分类号： H05K3/3436 , H01L23/49827 , H01L23/49833 , H01L2224/16225 , H01L2924/00014 , H01L2924/01078 , H01L2924/01322 , H01L2924/15311 , H01L2924/15312 , H05K3/284 , H05K2201/049 , H05K2201/10378 , H05K2201/10977 , H05K2203/041 , Y02P70/613 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/53174 , H01L2224/0401
摘要： The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.

4. 发明授权

US06306751B1 Apparatus and method for improving ball joints in semiconductor packages 有权
标题翻译：用于改善半导体封装中的球接头的装置和方法
公开(公告)号：US06306751B1
公开(公告)日：2001-10-23
申请号：US09406308
申请日：1999-09-27
申请人： Sunil A. Patel , Chok J. Chia , Kishor V. Desai
发明人： Sunil A. Patel , Chok J. Chia , Kishor V. Desai
IPC分类号： H01L2144
CPC分类号： H01L23/49816 , H01L21/288 , H01L21/4853 , H01L2924/0002 , H01L2924/00
摘要： Provided is an apparatus and method for modifying the manufacture of chip carrier bond pads to increase the quality and reliability of semiconductor packages and ball joints in particular. This is accomplished by minimizing the corrosion of the barrier metal layer on the functional bond pads during gold deposition with the use of sacrificial pads electrically connected with the functional bond pads. According to one embodiment of the invention, a semiconductor package has copper conductive pads on a substrate that are exposed through a dielectric. Both functional and sacrificial (nonfunctional) copper conductive pads are provided. A barrier metal layer composed of nickel is electrolessly plated onto these conductive pads, and a bond metal layer of gold is deposited onto the nickel using electroless, generally immersion, gold plating. The surface area of the nickel on the sacrificial pads is less than that on the functional pads, and the nickel on the sacrificial pads corrodes first during electroless gold deposition. Without nickel corrosion on the functional bond pad, gold can more uniformly be deposited on the surface of the nickel layer. A eutectic solderable material placed on the gold can form a uniform bond with the nickel because the nickel on the functional bond pad is largely corrosion free.
摘要翻译：提供了一种用于修改芯片载体接合焊盘的制造以提高半导体封装和球接头的质量和可靠性的装置和方法。这是通过使用与功能接合焊盘电连接的牺牲垫来最小化金沉积期间功能性接合焊盘上的阻挡金属层的腐蚀。根据本发明的一个实施例，半导体封装在衬底上具有通过电介质暴露的铜导电焊盘。提供功能和牺牲（非功能）铜导电焊盘。由镍构成的阻挡金属层被无电镀在这些导电焊盘上，并且使用化学镀，通常浸入镀金将金的粘结金属层沉积到镍上。牺牲焊盘上的镍的表面积小于功能焊盘上的镍的表面积，并且在无电镀金沉积期间，牺牲焊盘上的镍首先被腐蚀。在功能性接合焊盘上没有镍腐蚀，金可以更均匀地沉积在镍层的表面上。放置在金上的共晶可焊材料可以与镍形成均匀的结合，因为功能性接合焊盘上的镍很大程度上是无腐蚀的。

5. 发明授权

US6166434A Die clip assembly for semiconductor package 失效
标题翻译：用于半导体封装的芯片组件
公开(公告)号：US6166434A
公开(公告)日：2000-12-26
申请号：US935583
申请日：1997-09-23
申请人： Kishor V. Desai , Sunil A. Patel , John P. McCormick
发明人： Kishor V. Desai , Sunil A. Patel , John P. McCormick
IPC分类号： H01L21/56 , H01L23/04 , H01L23/12
CPC分类号： H01L21/563 , H01L23/04 , H01L24/29 , H01L24/32 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/00 , H01L2924/3512 , H01L2224/0401
摘要： Provided is a die clip for use in semiconductor flip chip packaging as a replacement for the conventional combination of a heat spreader and stiffener, a packaging method using the die clip, and a semiconductor package incorporating the die clip. In a preferred embodiment, the die clip is a piece of high modulus, high thermal conductivity material shaped to attach over a die on the surface of a packaging substrate. The die clip closely engages the die while leaving some space open around the perimeter to provide access to the die. An underfill material may then be dispensed into the gap between the die and the substrate through an opening in the die clip. The underfill material is then cured, the die clip providing a heat sink and keeping the die and substrate flat and immobile during and after the curing process. A BGA process may then be used to apply solder balls to the underside of the substrate for subsequent bonding of the package to a circuit board for use.
摘要翻译：提供了一种用于半导体倒装芯片封装的芯片夹，作为热扩散器和加强件的常规组合的替代品，使用该芯片夹的封装方法以及并入该夹具的半导体封装。在一个优选实施例中，模夹是一片高模量，高导热性的材料，其被成形为附着在包装基底的表面上的模具上。模夹紧密地接合模具，同时在周边周围留出一些空间以提供对模具的接近。然后可以通过模夹中的开口将底部填充材料分配到模具和基板之间的间隙中。然后固化底部填充材料，模具夹提供散热器并且在固化过程中和之后使模具和基底保持平坦且不变。然后可以使用BGA工艺将焊球施加到衬底的下侧，以便随后将封装连接到电路板以供使用。

6. 发明授权

US6002171A Integrated heat spreader/stiffener assembly and method of assembly for semiconductor package 失效
标题翻译：集成散热器/加强件组件及半导体封装的组装方法
公开(公告)号：US6002171A
公开(公告)日：1999-12-14
申请号：US935834
申请日：1997-09-22
申请人： Kishor V. Desai , Sunil A. Patel , John P. McCormick
发明人： Kishor V. Desai , Sunil A. Patel , John P. McCormick
IPC分类号： H01L23/367 , H01L23/10 , H01L23/34
CPC分类号： H01L23/3675 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/01322 , H01L2924/15311
摘要： Provided is a multi-piece integrated heat spreader/stiffener assembly which is bonded to the substrate and die in a semiconductor package following electrical bonding of the die to the substrate, a packaging method using the integrated heat spreader/stiffener, and a semiconductor package incorporating the integrated heat spreader/stiffener. In a preferred embodiment, the integrated heat spreader/stiffener assembly has two pieces, both composed of a high modulus, high thermal conductivity material shaped to attach to each other and a die on the surface of a packaging substrate. A first piece of this assembly is bonded to the substrate surface adjacent to an electrically connected die and to the top surface of the die prior to the dispensation and curing of underfill material which provides the mechanical connection between the die and the substrate. With the first piece of the assembly in place, access may still be had to at least one edge of the die to dispense and cure the underfill epoxy. Once the underfill material is cured by heating, the second piece of the assembly is placed and bonded on the substrate either abutting or overlapping with the first piece. A ball grid array (BGA) process may then be used to apply solder balls to the underside of the substrate for subsequent bonding of the package to a circuit board for use.
摘要翻译：提供了一种多件式集成散热器/加强件组件，其在将模具电连接到基板上之后，将半导体封装中的基板和芯片接合，使用集成散热器/加强件的封装方法以及包含集成散热器/加强筋。在一个优选实施例中，集成的散热器/加强件组件具有两个部件，两部分由高模量，高热导率的材料构成，彼此相互连接并在封装基板的表面上形成一个模具。该组件的第一部分在与电连接的模具相邻的基板表面上粘合到模具的顶部表面，在分配和固化底部填充材料之前，其提供了管芯和基板之间的机械连接。随着组装的第一块到位，仍然可以进入模具的至少一个边缘以分配和固化底部填充环氧树脂。一旦底部填充材料通过加热固化，则组件的第二块被放置并结合到基板上，与第一块邻接或重叠。然后可以使用球栅阵列（BGA）工艺将焊球施加到衬底的下侧，用于随后将封装结合到电路板以供使用。

7. 发明授权

US08772946B2 Reduced stress TSV and interposer structures 有权
标题翻译：减少应力TSV和插入结构
公开(公告)号：US08772946B2
公开(公告)日：2014-07-08
申请号：US13492064
申请日：2012-06-08
申请人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
发明人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/34 , H01L21/76841 , H01L21/76883 , H01L21/76885 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05558 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/1134 , H01L2224/1147 , H01L2224/13082 , H01L2224/13083 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/13565 , H01L2224/32105 , H01L2924/00011 , H01L2924/01322 , H01L2924/07811 , H01L2924/12042 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/81805
摘要： A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.
摘要翻译：部件可以包括在基板的开口内延伸的基板和导电通孔。基底可以具有第一和第二相对表面。开口可以从第一表面延伸到第二表面，并且可以具有远离第一表面延伸的内壁。电介质材料可以在内壁暴露。导电通孔可以在邻近第一表面的开口内限定释放通道。释放通道可以具有在与第一表面平行且在五微米以内的平面的方向上离内壁的第一距离内的边缘，第一距离是最小宽度的一微米和百分之五的最小宽度在飞机上开了边缘可以沿着内壁延伸以跨越内壁的圆周的至少百分之五。

8. 发明申请

US20130328186A1 REDUCED STRESS TSV AND INTERPOSER STRUCTURES 有权
标题翻译：减少应力TSV和间接结构
公开(公告)号：US20130328186A1
公开(公告)日：2013-12-12
申请号：US13492064
申请日：2012-06-08
申请人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
发明人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
IPC分类号： H01L23/48 , H01L21/28 , H01L23/498
CPC分类号： H01L23/34 , H01L21/76841 , H01L21/76883 , H01L21/76885 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05558 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/1134 , H01L2224/1147 , H01L2224/13082 , H01L2224/13083 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/13565 , H01L2224/32105 , H01L2924/00011 , H01L2924/01322 , H01L2924/07811 , H01L2924/12042 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/81805
摘要： A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.
摘要翻译：部件可以包括在基板的开口内延伸的基板和导电通孔。基底可以具有第一和第二相对表面。开口可以从第一表面延伸到第二表面，并且可以具有远离第一表面延伸的内壁。电介质材料可以在内壁暴露。导电通孔可以在邻近第一表面的开口内限定释放通道。释放通道可以具有在与第一表面平行且在五微米以内的平面的方向上离内壁的第一距离内的边缘，第一距离是最小宽度的一微米和百分之五的最小宽度在飞机上开了边缘可以沿着内壁延伸以跨越内壁的圆周的至少百分之五。

9. 发明授权

US07727781B2 Manufacture of devices including solder bumps 有权
标题翻译：制造包括焊料凸点的器件
公开(公告)号：US07727781B2
公开(公告)日：2010-06-01
申请号：US12220182
申请日：2008-07-22
申请人： Joze Eura Antol , Kishor V. Desai , John William Osenbach , Brian Thomas Vaccaro
发明人： Joze Eura Antol , Kishor V. Desai , John William Osenbach , Brian Thomas Vaccaro
IPC分类号： G01L31/26 , H01L21/66
CPC分类号： H05K3/3452 , H05K3/3457 , H05K2201/099 , H05K2203/0271 , H05K2203/162
摘要： Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.
摘要翻译：焊接接头（例如印刷电路板焊盘处的接头）的典型测试尚未被证明完全可以预测这种接头的最终性能。已经发现，这种缺乏可靠性至少部分地是由于这些焊盘在测试期间失去与下面的衬底的粘附或分层的倾向。相比之下，这种情况并不是典型的设备使用期间引起的现象。为了消除这种不可靠性的原因，测试结构与制造设备批次一起进行。使用相同的焊盘处理，并且焊盘尺寸在测试结构中大大扩大。测试结构用于预测批次中的设备的性能，然后相应地处理批次。

10. 发明授权

US06552266B2 High performance chip packaging and method 有权
公开(公告)号：US06552266B2
公开(公告)日：2003-04-22
申请号：US09770913
申请日：2001-01-26
申请人： Timothy F. Carden , Glenn O. Dearing , Kishor V. Desai , Stephen R. Engle , Randall Stutzman , George H. Thiel
发明人： Timothy F. Carden , Glenn O. Dearing , Kishor V. Desai , Stephen R. Engle , Randall Stutzman , George H. Thiel
IPC分类号： H01L2302
CPC分类号： H01L23/10 , H01L21/50 , H01L2224/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01078 , H01L2924/15311 , H01L2924/16195 , Y10T29/4913 , Y10T29/49144 , Y10T29/49149 , Y10T29/49169
摘要： A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board.

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