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    • 4. 发明授权
    • Apparatus and method for guest and root register sharing in a virtual machine
    • 在虚拟机中访客和根寄存器共享的装置和方法
    • US09086906B2
    • 2015-07-21
    • US13436654
    • 2012-03-30
    • Sanjay PatelRanjit Joseph Rozario
    • Sanjay PatelRanjit Joseph Rozario
    • G06F9/455
    • G06F9/4555
    • A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.
    • 计算机可读存储介质包括可执行指令,以定义具有访客模式控制寄存器的处理器,所述访客模式控制寄存器支持由访客模式控制寄存器中指定的访客上下文定 访客模式控制寄存器包括一个控制位,用于指定访客阻止寄存器状态和共享寄存器状态。 根模式控制寄存器支持在根模式控制寄存器中指定的根上下文定义的根模式操作行为。 根模式控制寄存器包括用于启用复制寄存器状态访问和共享寄存器状态访问的控制位。 访客环境和根本环境支持硬件资源的虚拟化,使得支持多个应用的​​多个操作系统由硬件资源执行。
    • 7. 发明授权
    • Resource sharing to reduce implementation costs in a multicore processor
    • 资源共享以降低多核处理器中的实施成本
    • US08195883B2
    • 2012-06-05
    • US12694877
    • 2010-01-27
    • Prashant JainYoganand ChillarigeSandip DasShukur Moulali PathanSrinivasan R. IyengarSanjay Patel
    • Prashant JainYoganand ChillarigeSandip DasShukur Moulali PathanSrinivasan R. IyengarSanjay Patel
    • G06F13/00
    • G06F12/0811G06F12/0813
    • A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.
    • 处理器可以包括几个处理器核心,每个处理器核心包括相应的更高级别的高速缓存; 包括几个标签单元的低级缓存,每个标签单元包括多个控制器,其中每个控制器对应于被配置为存储数据的相应缓存组,并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。 控制器可以共享对耦合到互连网络的互连出口端口的访问,并且可以生成多个并发请求以经由共享端口传送数据,其中每个请求去往相应的核心,并且其中端口的数据路径宽度 小于多个请求的组合宽度。 给定标签单元可以在控制器之间仲裁以访问共享端口,使得请求被串行地发送到相应的核心而不是同时发送。
    • 9. 发明授权
    • High speed semiconductor optical modulator
    • 高速半导体光调制器
    • US07672553B2
    • 2010-03-02
    • US11681070
    • 2007-03-01
    • Douglas M. GillChristopher D. W. JonesSanjay PatelMahmoud RasrasNils G. Weimann
    • Douglas M. GillChristopher D. W. JonesSanjay PatelMahmoud RasrasNils G. Weimann
    • G02B6/26
    • G02F1/025G02F2001/0152
    • The present invention provides an optical waveguide modulator. In one embodiment, the optical waveguide modulator includes a semiconductor planar optical waveguide core and doped semiconductor connecting paths located adjacent opposite sides of the core and capable of applying a voltage across the core. The optical waveguide core and connecting paths form a structure having back-to-back PN semiconductor junctions. In another embodiment, the optical waveguide modulator includes a semiconductor optical waveguide core including a ridge portion wherein the ridge portion has at least one PN semiconductor junction located therein. The optical waveguide modulator also includes one or more doped semiconductor connecting paths located laterally adjacent the ridge portion and capable of applying a voltage to the ridge portion.
    • 本发明提供一种光波导调制器。 在一个实施例中,光波导调制器包括半导体平面光波导芯和与芯相邻的相邻侧面的掺杂半导体连接路径,并能跨越芯施加电压。 光波导芯和连接路径形成具有背对背PN半导体结的结构。 在另一个实施例中,光波导调制器包括半导体光波导芯,其包括脊部,其中脊部具有位于其中的至少一个PN半导体结。 光波导调制器还包括一个或多个掺杂的半导体连接路径,其位于横向邻近脊部分并且能够向脊部分施加电压。
    • 10. 发明申请
    • INTEGRATED OPTOELECTRONIC SYSTEM FOR AUTOMATIC CALIBRATION OF AN OPTICAL DEVICE
    • 用于自动校准光学器件的集成光电系统
    • US20090161113A1
    • 2009-06-25
    • US11960017
    • 2007-12-19
    • Young-Kai ChenSanjay PatelMahmoud RasrasKun-Yii Tu
    • Young-Kai ChenSanjay PatelMahmoud RasrasKun-Yii Tu
    • G01B9/02
    • G02B6/12007G02B6/29353G02B6/29395G02F1/0147G02F2203/15
    • An apparatus and method for automated calibration of an optical device are disclosed. The apparatus is an integrated optoelectronic system that includes input and output optical waveguides, a tunable optical device, an optical source, an optical detector, and an electronic controller formed on a single substrate. The tunable optical device has one or more tuning elements for varying one or more characteristics of the device. The optical source is coupled to the input waveguide for providing a calibration signal to the device. The optical detector is coupled to the output optical waveguide for measuring an intensity of the optical signal output by the device in response to receiving the calibration signal. The electronic controller is configured to perform a calibration of the device by varying a parameter of each tuning element and to receive intensity measurements of the optical signal output by the device as a function of the varied parameter.
    • 公开了一种用于光学装置的自动校准的装置和方法。 该装置是集成光电系统,其包括输入和输出光波导,可调谐光学装置,光源,光学检测器和形成在单个基板上的电子控制器。 可调光学器件具有用于改变器件的一个或多个特性的一个或多个调谐元件。 光源耦合到输入波导,以向设备提供校准信号。 光学检测器耦合到输出光波导,用于响应于接收到校准信号来测量器件输出的光信号的强度。 电子控制器被配置为通过改变每个调谐元件的参数来执行设备的校准,并且根据变化的参数来接收设备输出的光信号的强度测量值。