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1. 发明申请

US20060157754A1 Semiconductor device including high-K insulating layer and method of manufacturing the same 有权
标题翻译：包括高K绝缘层的半导体器件及其制造方法
公开(公告)号：US20060157754A1
公开(公告)日：2006-07-20
申请号：US11335431
申请日：2006-01-18
申请人： Sang-Hun Jeon , Sung-Kyu Choi , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Ho Park , Jeong-Hee Han , Sang-Moo Choi
发明人： Sang-Hun Jeon , Sung-Kyu Choi , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Ho Park , Jeong-Hee Han , Sang-Moo Choi
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/02148 , H01L21/02156 , H01L21/02159 , H01L21/28282 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/792
摘要： A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.
摘要翻译：半导体存储器件，第一掺杂剂区域和第二掺杂剂区域，设置在半导体衬底中的第一掺杂区域和第二掺杂剂区域，与第一掺杂区域和第二掺杂剂区域接触设置的绝缘层，绝缘层包括选自Hf，Zr，Y和Ln的材料以及设置在绝缘层上的栅电极层。

2. 发明授权

US07456468B2 Semiconductor device including high-k insulating layer and method of manufacturing the same 有权
标题翻译：包括高k绝缘层的半导体器件及其制造方法
公开(公告)号：US07456468B2
公开(公告)日：2008-11-25
申请号：US11335431
申请日：2006-01-18
申请人： Sang-Hun Jeon , Sung-Kyu Choi , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Ho Park , Jeong-Hee Han , Sang-Moo Choi
发明人： Sang-Hun Jeon , Sung-Kyu Choi , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Ho Park , Jeong-Hee Han , Sang-Moo Choi
IPC分类号： H01L29/792
CPC分类号： H01L21/02148 , H01L21/02156 , H01L21/02159 , H01L21/28282 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/792
摘要： A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.
摘要翻译：半导体存储器件，第一掺杂剂区域和第二掺杂剂区域，设置在半导体衬底中的第一掺杂区域和第二掺杂剂区域，与第一掺杂区域和第二掺杂剂区域接触设置的绝缘层，绝缘层包括选自Hf，Zr，Y和Ln的材料以及设置在绝缘层上的栅电极层。

3. 发明授权

US07670916B2 Semiconductor device doped with Sb, Ga, or Bi and method of manufacturing the same 有权
标题翻译：用Sb，Ga或Bi掺杂的半导体器件及其制造方法
公开(公告)号：US07670916B2
公开(公告)日：2010-03-02
申请号：US12417432
申请日：2009-04-02
申请人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
发明人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/0843 , H01L29/167 , H01L29/792
摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.
摘要翻译：半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。

4. 发明授权

US07531865B2 Semiconductor device doped with Sb, Ga or Bi and method of manufacturing the same 有权
标题翻译：用Sb，Ga或Bi掺杂的半导体器件及其制造方法
公开(公告)号：US07531865B2
公开(公告)日：2009-05-12
申请号：US11333959
申请日：2006-01-17
申请人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
发明人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
IPC分类号： H01L29/788
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/0843 , H01L29/167 , H01L29/792
摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.
摘要翻译：半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。

5. 发明申请

US20060192246A1 Semiconductor memory device that uses metal nitride as trap site and method of manufacturing the same 审中-公开
标题翻译：使用金属氮化物作为陷阱位置的半导体存储器件及其制造方法
公开(公告)号：US20060192246A1
公开(公告)日：2006-08-31
申请号：US11365114
申请日：2006-02-28
申请人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sang-Moo Choi
发明人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sang-Moo Choi
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： B82Y10/00 , H01L29/40117 , H01L29/42332 , H01L29/792
摘要： In one embodiment, a memory device includes a gate structure comprising a metal nitride material in a charge storing layer on a semiconductor substrate. The gate structure is disposed between a first dopant region and a second dopant region formed on the semiconductor substrate. The metal nitride material is structured to function as a trap site for trapping a charge.
摘要翻译：在一个实施例中，存储器件包括在半导体衬底上的电荷存储层中包括金属氮化物材料的栅极结构。栅极结构设置在形成在半导体衬底上的第一掺杂区域和第二掺杂区域之间。金属氮化物材料被构造成用作捕获电荷的陷阱位置。

6. 发明申请

US20060157777A1 Semiconductor device doped with Sb,Ga or Bi and method of manufacturing the same 有权
标题翻译：用Sb，Ga或Bi掺杂的半导体器件及其制造方法
公开(公告)号：US20060157777A1
公开(公告)日：2006-07-20
申请号：US11333959
申请日：2006-01-17
申请人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
发明人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/0843 , H01L29/167 , H01L29/792
摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.
摘要翻译：半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。

7. 发明申请

US20060186462A1 Nonvolatile memory device and method of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20060186462A1
公开(公告)日：2006-08-24
申请号：US11357329
申请日：2006-02-21
申请人： Jeong-Hee Han , Ju-Hyung Kim , Chung-Woo Kim , Sang-Hun Jeon , Youn-Seok Jeong , Seung-Hyun Lee
发明人： Jeong-Hee Han , Ju-Hyung Kim , Chung-Woo Kim , Sang-Hun Jeon , Youn-Seok Jeong , Seung-Hyun Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L29/513 , H01L29/792
摘要： Provided are example embodiments of fabrication methods and resulting structures suitable for use in nonvolatile memory devices formed on semiconductor substrates. The example embodiments of the gate structures include a first insulating film formed on the semiconductor substrate, a storage node formed on the first insulating film for storing charges, a second insulating film formed on the storage node, a third insulating film formed on the second insulating film, and a gate electrode formed on the third insulating film. The insulating films are selected whereby the dielectric constant of one or both of the second and third insulating films is greater than the dielectric constant of the first insulating film.
摘要翻译：提供了适用于形成在半导体衬底上的非易失性存储器件中的制造方法和结果结构的示例性实施例。栅极结构的示例实施例包括形成在半导体衬底上的第一绝缘膜，形成在用于存储电荷的第一绝缘膜上的存储节点，形成在存储节点上的第二绝缘膜，形成在第二绝缘层上的第三绝缘膜膜和形成在第三绝缘膜上的栅电极。选择绝缘膜，由此第二和第三绝缘膜中的一个或两个的介电常数大于第一绝缘膜的介电常数。

8. 发明授权

US08022410B2 Thin film transistors 有权
标题翻译：薄膜晶体管
公开(公告)号：US08022410B2
公开(公告)日：2011-09-20
申请号：US12497852
申请日：2009-07-06
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L29/786
CPC分类号： H01L29/41733 , H01L27/1292 , H01L29/42384
摘要： A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.
摘要翻译：薄膜晶体管包括具有栅电极，栅极绝缘层和沟道层的层结构。源极线可以接触沟道层，并且可以沿着与栅电极交叉的方向延伸。源极线可以部分地与栅电极重叠，使得与栅电极重叠的源极线的两侧可以完全位于栅电极的两侧之间。漏极线可以与沟道层接触并且可以与源极线隔开通道长度。漏极线可以具有与源极线对称的结构。可以减小栅电极，源极线和漏极线之间的重叠区域，使得薄膜晶体管可以确保高的截止频率。

9. 发明申请

US20100301425A1 SEMICONDUCTOR DEVICE HAVING A GATE CONTACT STRUCTURE CAPABLE OF REDUCING INTERFACIAL RESISTANCE 有权
标题翻译：具有能够降低界面电阻的门接触结构的半导体器件
公开(公告)号：US20100301425A1
公开(公告)日：2010-12-02
申请号：US12856295
申请日：2010-08-13
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的接触插塞使多晶硅层通过开口接触。

10. 发明申请

US20090259839A1 SECURITY AUTHENTICATION SYSTEM AND METHOD 有权
标题翻译：安全认证系统和方法
公开(公告)号：US20090259839A1
公开(公告)日：2009-10-15
申请号：US12098642
申请日：2008-04-07
申请人： Young-Sik Jung , In-Hyuk Choi , Min-Chol Song , Jong-Won Paek , Sung-Ho Lee , Sang-Hee Bang , Sang-Hun Jeon
发明人： Young-Sik Jung , In-Hyuk Choi , Min-Chol Song , Jong-Won Paek , Sung-Ho Lee , Sang-Hee Bang , Sang-Hun Jeon
IPC分类号： H04L9/32 , G06F15/16
CPC分类号： H04L63/08 , G06F21/33 , H04L9/321 , H04L9/3226 , H04L9/3271 , H04L63/105 , H04L63/20
摘要： Authentication system and method are provided. The authentication system includes: a server configured to provide at least two security levels and configured to transmit one of at least two security modules corresponding to the security level of a user terminal, via communications network, to the user terminal based, at least in part, upon an environment of the user terminal; and an authentication server communicatively linked with the server and configured to perform a user authentication in response to a user authentication request from the user terminal. Accordingly, various hackings can be prevented and the user authentication can be accomplished with user's convenience and security.
摘要翻译：提供认证系统和方法。所述认证系统包括：被配置为提供至少两个安全级别并被配置为至少部分地通过通信网络将与用户终端的安全级别对应的至少两个安全模块中的一个发送到所述用户终端的服务器在用户终端的环境下; 以及与所述服务器通信地链接并被配置为响应于来自所述用户终端的用户认证请求执行用户认证的认证服务器。因此，可以防止各种黑客攻击，并且可以用户的方便和安全性来实现用户认证。

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