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1. 发明授权

US07531865B2 Semiconductor device doped with Sb, Ga or Bi and method of manufacturing the same 有权
标题翻译：用Sb，Ga或Bi掺杂的半导体器件及其制造方法
公开(公告)号：US07531865B2
公开(公告)日：2009-05-12
申请号：US11333959
申请日：2006-01-17
申请人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
发明人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
IPC分类号： H01L29/788
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/0843 , H01L29/167 , H01L29/792
摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.
摘要翻译：半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。

2. 发明申请

US20060157777A1 Semiconductor device doped with Sb,Ga or Bi and method of manufacturing the same 有权
标题翻译：用Sb，Ga或Bi掺杂的半导体器件及其制造方法
公开(公告)号：US20060157777A1
公开(公告)日：2006-07-20
申请号：US11333959
申请日：2006-01-17
申请人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
发明人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/0843 , H01L29/167 , H01L29/792
摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.
摘要翻译：半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。

3. 发明授权

US07670916B2 Semiconductor device doped with Sb, Ga, or Bi and method of manufacturing the same 有权
标题翻译：用Sb，Ga或Bi掺杂的半导体器件及其制造方法
公开(公告)号：US07670916B2
公开(公告)日：2010-03-02
申请号：US12417432
申请日：2009-04-02
申请人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
发明人： Sang-Hun Jeon , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Kweon Baek , Sang-Moo Choi
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/0843 , H01L29/167 , H01L29/792
摘要： A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.
摘要翻译：半导体存储器件包括在半导体衬底中的第一掺杂区域和第二掺杂剂区域，掺杂有Sb，Ga和Bi组成的组的第一掺杂区域和第二掺杂剂区域。半导体存储器件包括与第一掺杂剂区域和第二掺杂剂区域接触设置的绝缘层和与绝缘层接触设置的栅极电极层。

4. 发明申请

US20090072294A1 Method of manufacturing a non-volatile memory device 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090072294A1
公开(公告)日：2009-03-19
申请号：US11974636
申请日：2007-10-15
申请人： Sang-Ryol Yang , Sung-Kweon Baek , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang
发明人： Sang-Ryol Yang , Sung-Kweon Baek , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of manufacturing a non-volatile memory device employing a relatively thin polysilicon layer as a floating gate is disclosed, wherein a tunnel oxide layer is formed on a substrate and a polysilicon layer having a thickness of about 35 Å to about 200 Å is then formed on the tunnel oxide layer using a trisilane (Si3H8) gas as a silicon source gas. The tunnel oxide layer and the polysilicon layer are then patterned into a tunnel oxide layer pattern and a polysilicon layer pattern, respectively. A dielectric layer and a conductive layer corresponding to a control gate are subsequently formed on the polysilicon layer pattern. The polysilicon layer is formed using trisilane (Si3H8) gas as a result of which the polysilicon layer may be formed to have a relatively thin thickness while maintaining a thickness uniformity and realizing a superior morphology thus producing a floating gate having enhanced performance.
摘要翻译：公开了一种使用相对薄的多晶硅层作为浮动栅极的非易失性存储器件的制造方法，其中在衬底上形成隧道氧化物层，然后形成厚度为约至大约的厚度的多晶硅层使用丙硅烷（Si 3 H 8）气体作为硅源气体在隧道氧化物层上形成。然后将隧道氧化物层和多晶硅层分别图案化为隧道氧化物层图案和多晶硅层图案。随后在多晶硅层图案上形成对应于控制栅的电介质层和导电层。使用丙硅烷（Si 3 H 8）气体形成多晶硅层，结果可以形成多晶硅层以具有相对较薄的厚度，同时保持厚度均匀性并实现优异的形态，从而产生具有增强性能的浮栅。

5. 发明申请

US20080085584A1 OXIDATION/HEAT TREATMENT METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES 审中-公开
标题翻译：制造非易失性存储器件的氧化/热处理方法
公开(公告)号：US20080085584A1
公开(公告)日：2008-04-10
申请号：US11857824
申请日：2007-09-19
申请人： Young-Jin Noh , Chul-Sung Kim , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang , Sung-Kweon Baek
发明人： Young-Jin Noh , Chul-Sung Kim , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang , Sung-Kweon Baek
IPC分类号： H01L21/336
CPC分类号： H01L21/28247 , H01L29/40114
摘要： Methods of manufacturing non-volatile memory devices are disclosed which may at least partially cure etch damage and may at least partially remove defect sites in gate structures of the devices caused during manufacturing of the devices. An exemplary method of manufacturing a non-volatile memory device includes forming a gate structure on a substrate, the gate structure including a control gate electrode, a blocking layer pattern, a floating gate electrode, and a tunnel insulating layer pattern. An oxidation process is performed that at least partially cures damage caused to the substrate and to the gate structure during formation of the gate structure. A first heat treatment is performed under a gas atmosphere including nitrogen to at least partially remove defect sites on the gate structure caused by the oxidation process. A second heat treatment is performed under a gas atmosphere including chlorine to at least partially remove remaining defect sites on the gate structure caused by the oxidation process.
摘要翻译：公开了制造非易失性存储器件的方法，其可以至少部分地固化蚀刻损伤，并且可以至少部分地去除在器件的制造期间引起的器件的栅极结构中的缺陷位置。制造非易失性存储器件的示例性方法包括在衬底上形成栅极结构，栅极结构包括控制栅电极，阻挡层图案，浮栅电极和隧道绝缘层图案。进行氧化处理，其至少部分地固化在栅极结构形成期间对衬底和栅极结构的损伤。在包括氮气的气体气氛下进行第一热处理，以至少部分地去除由氧化过程引起的栅极结构上的缺陷部位。在包括氯的气体气氛下进行第二热处理，以至少部分地去除由氧化过程引起的栅极结构上的剩余缺陷部位。

6. 发明授权

US07473959B2 Non-volatile semiconductor memory devices and methods of fabricating the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07473959B2
公开(公告)日：2009-01-06
申请号：US11601505
申请日：2006-11-17
申请人： Sung-Hae Lee , Chang-Hyun Lee , Ki-Hyun Hwang , Sung-Kweon Baek , Kwang-Min Park
发明人： Sung-Hae Lee , Chang-Hyun Lee , Ki-Hyun Hwang , Sung-Kweon Baek , Kwang-Min Park
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L27/115 , H01L29/513
摘要： Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation film. The blocking insulation film includes a stacked film structure of a high-dielectric film and a barrier insulation film. The high-dielectric film has a first potential barrier relative to the charge-trapping layer. The barrier insulation film has a second potential barrier relative to the charge-trapping layer which is higher than the first potential barrier. The blocking insulation film has a thickness in a range of about 5 Å to about 15 Å.
摘要翻译：公开了非易失性存储器件和制造非易失性存储器件的相关方法。非易失性存储器件包括半导体衬底上的隧道绝缘膜，隧道绝缘膜上的电荷俘获层，电荷俘获层上的块绝缘膜和阻挡绝缘膜上的栅电极。阻挡绝缘膜包括高电介质膜和阻挡绝缘膜的叠层膜结构。高电介质膜相对于电荷俘获层具有第一势垒。阻挡绝缘膜相对于高于第一势垒的电荷俘获层具有第二势垒。阻挡绝缘膜的厚度在约5至约15的范围内。

7. 发明授权

US07608509B2 Method of manufacturing a flash memory device having compensation members formed on edge portions of a tunnel oxide layer 有权
标题翻译：制造具有形成在隧道氧化物层的边缘部分上的补偿部件的闪存装置的方法
公开(公告)号：US07608509B2
公开(公告)日：2009-10-27
申请号：US11494439
申请日：2006-07-27
申请人： Chul-Sung Kim , Yu-Gyun Shin , Bon-Young Koo , Sung-Kweon Baek , Young-Jin Noh
发明人： Chul-Sung Kim , Yu-Gyun Shin , Bon-Young Koo , Sung-Kweon Baek , Young-Jin Noh
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42336
摘要： In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is formed on the insulation layer. The protruded upper portions of the preliminary isolation regions are removed to form isolation regions on the substrate and to expose sidewalls of the first conductive layer, and compensation members are formed on edge portions of the insulation layer. The compensation members may complement the edge portions of the insulation layer that have thicknesses substantially thinner than that of a center portion of the insulation layer, and may prevent deterioration of the insulation layer. Furthermore, the first conductive layer having a width substantially greater than that of the active region may enhance a coupling ratio of the semiconductor device. Thus, the semiconductor device may have improved electrical characteristics and reliability.
摘要翻译：在半导体器件和半导体器件的制造方法中，在衬底上形成具有突出的上部的预备隔离区以限定有源区。在有源区上形成绝缘层之后，在绝缘层上形成第一导电层。去除预分离区域的突出的上部，以在衬底上形成隔离区域并暴露第一导电层的侧壁，并且补偿构件形成在绝缘层的边缘部分上。补偿构件可以补充绝缘层的边缘部分，该边缘部分的厚度基本上比绝缘层的中心部分的厚度更薄，并且可以防止绝缘层的劣化。此外，具有基本上大于有源区的宽度的第一导电层可以增强半导体器件的耦合比。因此，半导体器件可以具有改善的电特性和可靠性。

8. 发明申请

US20080090354A1 Method of Manufacturing a Non-Volatile Memory Device 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080090354A1
公开(公告)日：2008-04-17
申请号：US11868195
申请日：2007-10-05
申请人： Sung-Kweon Baek , Bon-Young Koo , Chul-Sung Kim , Jung-Geun Jee , Young-Jin Noh
发明人： Sung-Kweon Baek , Bon-Young Koo , Chul-Sung Kim , Jung-Geun Jee , Young-Jin Noh
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/792
摘要： A method of manufacturing a non-volatile memory device, includes forming a tunnel isolation layer comprising an oxynitride on a substrate by a simultaneous oxidation and nitridation treatment in which an oxidation process and a nitridation process are simultaneously performed using a processing gas including oxygen and nitrogen. The method further includes performing first and second heat treatments to remove defect sites from the tunnel isolation layer in gas atmospheres including nitrogen (N) and chlorine (Cl), respectively and forming a gate structure on the tunnel isolation layer after the second heat treatment, and forming source/drain regions at surface portions of the substrate adjacent to the gate structure.
摘要翻译：一种制造非易失性存储器件的方法包括通过同时氧化和氮化处理在衬底上形成包含氧氮化物的隧道隔离层，其中使用包括氧和氮的处理气体同时进行氧化过程和氮化处理。该方法还包括进行第一和第二热处理以分别在包括氮（N）和氯（Cl）的气体环境中从隧道隔离层去除缺陷位点，并在第二热处理之后在隧道隔离层上形成栅结构，以及在与栅极结构相邻的衬底的表面部分处形成源极/漏极区域。

9. 发明申请

US20070063265A1 Non-volatile semiconductor memory devices and methods of fabricating the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070063265A1
公开(公告)日：2007-03-22
申请号：US11601505
申请日：2006-11-17
申请人： Sung-Hae Lee , Chang-Hyun Lee , Ki-Hyun Hwang , Sung-Kweon Baek , Kwang-Min Park
发明人： Sung-Hae Lee , Chang-Hyun Lee , Ki-Hyun Hwang , Sung-Kweon Baek , Kwang-Min Park
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L27/115 , H01L29/513
摘要： Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation film. The blocking insulation film includes a stacked film structure of a high-dielectric film and a barrier insulation film. The high-dielectric film has a first potential barrier relative to the charge-trapping layer. The barrier insulation film has a second potential barrier relative to the charge-trapping layer which is higher than the first potential barrier. The blocking insulation film has a thickness in a range of about 5 Å to about 15 Å.
摘要翻译：公开了非易失性存储器件和制造非易失性存储器件的相关方法。非易失性存储器件包括半导体衬底上的隧道绝缘膜，隧道绝缘膜上的电荷俘获层，电荷俘获层上的块绝缘膜和阻挡绝缘膜上的栅电极。阻挡绝缘膜包括高电介质膜和阻挡绝缘膜的叠层膜结构。高电介质膜相对于电荷俘获层具有第一势垒。阻挡绝缘膜相对于高于第一势垒的电荷俘获层具有第二势垒。阻挡绝缘膜的厚度在约5至约15的范围内。

10. 发明授权

US08008154B2 Methods of forming impurity containing insulating films and flash memory devices including the same 失效
标题翻译：形成含杂质的绝缘膜的方法和包括其的闪存器件的方法
公开(公告)号：US08008154B2
公开(公告)日：2011-08-30
申请号：US12188482
申请日：2008-08-08
申请人： Young-Jin Noh , Bon-Young Koo , Si-Young Choi , Ki-Hyun Hwang , Chul-Sung Kim , Sung-Kweon Baek , Jin-Hwa Heo
发明人： Young-Jin Noh , Bon-Young Koo , Si-Young Choi , Ki-Hyun Hwang , Chul-Sung Kim , Sung-Kweon Baek , Jin-Hwa Heo
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/28273 , H01L21/3145 , H01L21/31662
摘要： Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.
摘要翻译：形成绝缘膜的方法包括在基板上形成绝缘膜。使用第一组处理条件下的热处理将第一杂质注入绝缘膜，以在绝缘膜的下部形成第一杂质浓度峰。在与第一组处理条件不同的第二组处理条件下，使用热处理将第二杂质注入到绝缘膜中，以在绝缘膜的上部形成第二杂质浓度峰。注入第一杂质并注入第二杂质可以在不使用等离子体的情况下进行，并且第一杂质浓度峰可以高于第二杂质浓度峰。

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