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1. 发明申请

US20060259745A1 Processor having efficient function estimate instructions 失效
标题翻译：处理器具有有效的功能估计指令
公开(公告)号：US20060259745A1
公开(公告)日：2006-11-16
申请号：US11127848
申请日：2005-05-12
申请人： Sang Dhong , Gordon Fossum , Harm Hofstee , Brad Michael , Silvia Mueller , Hwa-Joon Oh
发明人： Sang Dhong , Gordon Fossum , Harm Hofstee , Brad Michael , Silvia Mueller , Hwa-Joon Oh
IPC分类号： G06F9/44
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： A preferred embodiment of the present invention provides a method, computer program product, and processor design for supporting high-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, a preferred embodiment of the present invention incurs significantly less overhead than would specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：本发明的优选实施例提供了一种用于支持高精度浮点函数估计的方法，计算机程序产品和处理器设计，其分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，本发明的优选实施例显着减少开销，同时仍保持均匀的FPU等待时间，这允许更简单的控制逻辑。

2. 发明申请

US20070061553A1 Byte Execution Unit for Carrying Out Byte Instructions in a Processor 审中-公开
标题翻译：在处理器中执行字节指令的字节执行单元
公开(公告)号：US20070061553A1
公开(公告)日：2007-03-15
申请号：US11555513
申请日：2006-11-01
申请人： Sang Dhong , Hwa-Joon Oh , Brad Michael , Silvia Mueller , Kevin Tran
发明人： Sang Dhong , Hwa-Joon Oh , Brad Michael , Silvia Mueller , Kevin Tran
IPC分类号： G06F9/44
CPC分类号： G06F9/30014 , G06F9/30036
摘要： A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.
摘要翻译：公开的字节执行单元接收字节指令信息和两个操作数，并且在一个或两个操作数上执行由字节指令信息指定的操作，从而产生结果。字节指令指定以字节为单位的计数值，平均字节操作，字节操作的绝对差值，或字节字节到半字操作。在一个实施例中，字节执行单元包括多个字节单元。每个字节单元包括多个总体计数器，两个压缩器单元，加法器输入多路复用器逻辑，加法器逻辑和结果多路复用器逻辑。描述了包括耦合到存储器系统的处理器的数据处理系统。处理器包括字节执行单元。存储器系统包括一个字节指令，其中字节指令指定字节操作中的计数值，平均字节操作，字节操作的绝对差值，或字节数字到半字操作。

3. 发明申请

US20050015576A1 Byte execution unit for carrying out byte instructions in a processor 失效
标题翻译：用于在处理器中执行字节指令的字节执行单元
公开(公告)号：US20050015576A1
公开(公告)日：2005-01-20
申请号：US10621908
申请日：2003-07-17
申请人： Sang Dhong , Hwa-Joon Oh , Brad Michael , Silvia Mueller , Kevin Tran
发明人： Sang Dhong , Hwa-Joon Oh , Brad Michael , Silvia Mueller , Kevin Tran
IPC分类号： G06F9/00 , G06F9/302
CPC分类号： G06F9/30014 , G06F9/30036
摘要： A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.
摘要翻译：公开的字节执行单元接收字节指令信息和两个操作数，并且在一个或两个操作数上执行由字节指令信息指定的操作，从而产生结果。字节指令指定以字节为单位的计数值，平均字节操作，字节操作的绝对差值，或字节字节到半字操作。在一个实施例中，字节执行单元包括多个字节单元。每个字节单元包括多个总体计数器，两个压缩器单元，加法器输入多路复用器逻辑，加法器逻辑和结果多路复用器逻辑。描述了包括耦合到存储器系统的处理器的数据处理系统。处理器包括字节执行单元。存储器系统包括一个字节指令，其中字节指令指定字节操作中的计数值，平均字节操作，字节操作的绝对差值，或字节数字到半字操作。

4. 发明申请

US20070186135A1 Processor system and methodology with background error handling feature 审中-公开
标题翻译：具有背景错误处理功能的处理器系统和方法
公开(公告)号：US20070186135A1
公开(公告)日：2007-08-09
申请号：US11351121
申请日：2006-02-09
申请人： Brian Flachs , H. Hofstee , John Liberty , Brad Michael
发明人： Brian Flachs , H. Hofstee , John Liberty , Brad Michael
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A processor system is disclosed that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. ECC hardware circuitry provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The disclosed methodology permits the detection and correction of soft single bit errors read from local memory in-line while using read modify write DMA circuit logic to correct local memory data. The disclosed methodology provides local memory data error detection and correction in a background memory scrub process without the need for additional in-line data logic.
摘要翻译：公开了一种在存储器管理电路内集成纠错码（ECC）检测和校正硬件的处理器系统。 ECC硬件电路提供与存储器数据读取和写入相结合的ECC数据位的检测，校正和生成。所公开的方法允许检测和校正从本地存储器在线读取的软单比特错误，同时使用读修改写DMA电路逻辑来校正本地存储器数据。所公开的方法在后台存储器擦除过程中提供本地存储器数据错误检测和校正，而不需要额外的在线数据逻辑。

5. 发明申请

US20060224869A1 Combination of forwarding/bypass network with history file 审中-公开
标题翻译：转发/旁路网络与历史文件的组合
公开(公告)号：US20060224869A1
公开(公告)日：2006-10-05
申请号：US11095908
申请日：2005-03-31
申请人： Brian Flachs , Brad Michael
发明人： Brian Flachs , Brad Michael
IPC分类号： G06F9/44
CPC分类号： G06F9/3842 , G06F9/3863 , G06F9/3867
摘要： An apparatus, a method, and a processor are provided for recovering the correct state of processor instructions in a processor. This apparatus contains a pipeline of latches, a register file, and a replay loop. The replay loop repairs incorrect results and inserts the repaired results back into the pipeline. A state machine detects incorrect results within the pipeline and sends the incorrect results to the replay loop. A correction module on the replay loop repairs the incorrect results and transmits the repaired results back into the pipeline. When an incorrect result enters the replay loop, a flush operation: ceases other operations within the pipeline; flushes the rest of the data results in the pipeline to the replay loop; opens the pipeline for the repaired results to be inserted; and eliminates any operations within the processor that would utilize the incorrect results.
摘要翻译：提供了一种用于在处理器中恢复处理器指令的正确状态的装置，方法和处理器。该设备包含一个锁存器流水线，一个寄存器文件和一个重放循环。重播循环修复不正确的结果，并将修复的结果插入管道。状态机在管道中检测不正确的结果，并将不正确的结果发送到重放循环。重播循环上的校正模块修复错误的结果，并将修复的结果发送回管道。当不正确的结果进入重放循环时，刷新操作：停止管道内的其他操作; 将流水线中的其余数据结果刷新到重放循环; 打开要插入的修复结果的管道; 并消除处理器内利用错误结果的任何操作。

6. 发明申请

US20060179277A1 System and method for instruction line buffer holding a branch target buffer 审中-公开
标题翻译：用于指示行缓冲器的系统和方法，保持分支目标缓冲区
公开(公告)号：US20060179277A1
公开(公告)日：2006-08-10
申请号：US11052502
申请日：2005-02-04
申请人： Brian Flachs , Brad Michael
发明人： Brian Flachs , Brad Michael
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30047 , G06F9/3804 , G06F9/3814
摘要： A system and method that maintains a relatively small Instruction Load Buffer (ILB) is maintained for scheduling instructions. Instructions are sent from Local Store (LS) to the ILB using either an inline prefetcher or a branch table buffer loader. In one embodiment, the prefetcher is a hardware-based prefetcher that fetches, in address order, the next instructions likely to be scheduled. In one embodiment, the predicted branch instructions are loaded as a result of a software program, such as a dispatcher, issuing a “load branch table buffer (loadbtb)” instruction. Predicted branch instructions are loaded in one area of the ILB and inline instructions are loaded in another area of the ILB. In one embodiment, the loadbtb loads the instruction line that includes the predicted branch target address as well as the instruction line that immediately follows the instruction line with the predicted branch target address.
摘要翻译：维护相对较小的指令加载缓冲器（ILB）的系统和方法被维护用于调度指令。使用内联预取器或分支表缓冲区加载器将本地存储（LS）发送到ILB。在一个实施例中，预取器是基于硬件的预取器，其以地址顺序提取可能被调度的下一个指令。在一个实施例中，作为诸如调度器的软件程序的结果，预测的分支指令被加载，发出“加载分支表缓冲器（loadbtb）”指令。预测的分支指令被加载到ILB的一个区域中，并且内联指令被加载到ILB的另一个区域中。在一个实施例中，loadbtb将包含预测的分支目标地址的指令行以及与预测的分支目标地址紧接在指令行之后的指令行一起加载。

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