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1. 发明申请

US20070061553A1 Byte Execution Unit for Carrying Out Byte Instructions in a Processor 审中-公开
标题翻译：在处理器中执行字节指令的字节执行单元
公开(公告)号：US20070061553A1
公开(公告)日：2007-03-15
申请号：US11555513
申请日：2006-11-01
申请人： Sang Dhong , Hwa-Joon Oh , Brad Michael , Silvia Mueller , Kevin Tran
发明人： Sang Dhong , Hwa-Joon Oh , Brad Michael , Silvia Mueller , Kevin Tran
IPC分类号： G06F9/44
CPC分类号： G06F9/30014 , G06F9/30036
摘要： A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.
摘要翻译：公开的字节执行单元接收字节指令信息和两个操作数，并且在一个或两个操作数上执行由字节指令信息指定的操作，从而产生结果。字节指令指定以字节为单位的计数值，平均字节操作，字节操作的绝对差值，或字节字节到半字操作。在一个实施例中，字节执行单元包括多个字节单元。每个字节单元包括多个总体计数器，两个压缩器单元，加法器输入多路复用器逻辑，加法器逻辑和结果多路复用器逻辑。描述了包括耦合到存储器系统的处理器的数据处理系统。处理器包括字节执行单元。存储器系统包括一个字节指令，其中字节指令指定字节操作中的计数值，平均字节操作，字节操作的绝对差值，或字节数字到半字操作。

2. 发明申请

US20050015576A1 Byte execution unit for carrying out byte instructions in a processor 失效
标题翻译：用于在处理器中执行字节指令的字节执行单元
公开(公告)号：US20050015576A1
公开(公告)日：2005-01-20
申请号：US10621908
申请日：2003-07-17
申请人： Sang Dhong , Hwa-Joon Oh , Brad Michael , Silvia Mueller , Kevin Tran
发明人： Sang Dhong , Hwa-Joon Oh , Brad Michael , Silvia Mueller , Kevin Tran
IPC分类号： G06F9/00 , G06F9/302
CPC分类号： G06F9/30014 , G06F9/30036
摘要： A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.
摘要翻译：公开的字节执行单元接收字节指令信息和两个操作数，并且在一个或两个操作数上执行由字节指令信息指定的操作，从而产生结果。字节指令指定以字节为单位的计数值，平均字节操作，字节操作的绝对差值，或字节字节到半字操作。在一个实施例中，字节执行单元包括多个字节单元。每个字节单元包括多个总体计数器，两个压缩器单元，加法器输入多路复用器逻辑，加法器逻辑和结果多路复用器逻辑。描述了包括耦合到存储器系统的处理器的数据处理系统。处理器包括字节执行单元。存储器系统包括一个字节指令，其中字节指令指定字节操作中的计数值，平均字节操作，字节操作的绝对差值，或字节数字到半字操作。

3. 发明申请

US20050114422A1 High performance implementation of exponent adjustment in a floating point design 失效
标题翻译：浮点设计中指数调整的高性能实现
公开(公告)号：US20050114422A1
公开(公告)日：2005-05-26
申请号：US10718303
申请日：2003-11-20
申请人： Sang Dhong , Silvia Mueller , Hwa-Joon Oh , Kevin Tran
发明人： Sang Dhong , Silvia Mueller , Hwa-Joon Oh , Kevin Tran
IPC分类号： G06F7/00 , G06F7/38 , G06F7/48 , G06F7/483 , G06F7/499 , G06F7/74
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/74
摘要： A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value. The exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the first incremented exponent value and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value. Either the exponent output value, the first incremented exponent output value, or the second exponent output value are then selected.
摘要翻译：一个浮点单元（FPU），产生一个校正信号和一个反向的前导零信号。指数逻辑被配置为生成指数值，第一递增指数值和第二递增指数值。指数调整和舍入逻辑，配置为接收指数值，第一递增指数值和第二递增指数值。指数调整和舍入逻辑还被配置为将反向引导零信号加到第一递增指数值和第二递增指数值，从而产生指数输出值，第一递增指数输出值和第二递增指数输出值。然后选择指数输出值，第一递增指数输出值或第二指数输出值。

4. 发明申请

US20060218388A1 Method and system for iSCSl boot 有权
标题翻译： iSCSl启动的方法和系统
公开(公告)号：US20060218388A1
公开(公告)日：2006-09-28
申请号：US11389980
申请日：2006-03-27
申请人： Uri Zur , Kan Fan , Murali Rajagopal , Kevin Tran
发明人： Uri Zur , Kan Fan , Murali Rajagopal , Kevin Tran
IPC分类号： G06F15/177
CPC分类号： G06F9/4416
摘要： Certain aspects of a method for iSCSI boot may include loading boot BIOS code from a host bus adapter or a network interface controller (NIC) by an iSCSI client device. A connection may be established to an iSCSI target by the iSCSI client device after loading the boot BIOS code. The boot BIOS code may be chained to at least one interrupt handler over iSCSI protocol. An operating system may be remotely booted from the iSCSI target by the iSCSI client device based on chaining the interrupt handler. An Internet protocol (IP) address and/or location of the iSCSI target may be received. At least one iSCSI connection may be initiated to the iSCSI target based on chaining at least one interrupt handler. The iSCSI target may be booted in real mode if at least one master boot record is located in the memory.
摘要翻译： iSCSI引导方法的某些方面可能包括通过iSCSI客户端设备从主机总线适配器或网络接口控制器（NIC）加载引导BIOS代码。在加载引导BIOS代码之后，iSCSI客户端设备可以建立到iSCSI目标的连接。引导BIOS代码可以通过iSCSI协议链接至少一个中断处理程序。基于链接中断处理程序，iSCSI客户端设备可以从iSCSI目标远程启动操作系统。可以接收iSCSI目标的因特网协议（IP）地址和/或位置。至少一个iSCSI连接可以基于链接至少一个中断处理程序发起到iSCSI目标。如果至少有一个主引导记录位于存储器中，iSCSI目标可能会以实模式引导。

5. 发明申请

US20100306521A1 METHOD AND SYSTEM FOR ISCSI BOOT IN WHICH AN ISCSI CLIENT LOADS BOOT CODE FROM A HOST BUS ADAPTER AND/OR NETWORK INTERFACE CARD 失效
标题翻译：用于ISCSI客户端的ISCSI引导的方法和系统负载来自主机总线适配器和/或网络接口卡的引导代码
公开(公告)号：US20100306521A1
公开(公告)日：2010-12-02
申请号：US12826075
申请日：2010-06-29
申请人： Uri El Zur , Kan Frankie Fan , Murali Rajagopal , Kevin Tran
发明人： Uri El Zur , Kan Frankie Fan , Murali Rajagopal , Kevin Tran
IPC分类号： G06F15/177
CPC分类号： G06F9/4416
摘要： Certain aspects of a method for iSCSI boot may include loading boot BIOS code from a host bus adapter or a network interface controller (NIC) by an iSCSI client device. A connection may be established to an iSCSI target by the iSCSI client device after loading the boot BIOS code. The boot BIOS code may be chained to at least one interrupt handler over iSCSI protocol. An operating system may be remotely booted from the iSCSI target by the iSCSI client device based on chaining the interrupt handler. An Internet protocol (IP) address and/or location of the iSCSI target may be received. At least one iSCSI connection may be initiated to the iSCSI target based on chaining at least one interrupt handler. The iSCSI target may be booted in real mode if at least one master boot record is located in the memory.
摘要翻译： iSCSI引导方法的某些方面可能包括通过iSCSI客户端设备从主机总线适配器或网络接口控制器（NIC）加载引导BIOS代码。在加载引导BIOS代码之后，iSCSI客户端设备可以建立到iSCSI目标的连接。引导BIOS代码可以通过iSCSI协议链接至少一个中断处理程序。基于链接中断处理程序，iSCSI客户端设备可以从iSCSI目标远程启动操作系统。可以接收iSCSI目标的因特网协议（IP）地址和/或位置。至少一个iSCSI连接可以基于链接至少一个中断处理程序发起到iSCSI目标。如果至少有一个主引导记录位于存储器中，iSCSI目标可能会以实模式引导。

6. 发明申请

US20170226467A1 MICROSCALE BIOPROCESSING SYSTEM AND METHOD FOR PROTEIN MANUFACTURING FROM HUMAN BLOOD 审中-公开
公开(公告)号：US20170226467A1
公开(公告)日：2017-08-10
申请号：US15329555
申请日：2015-07-31
申请人： Govind Rao , Yordan Kostov , Leah Tolosa , Kevin Tran , Monohar Pilli , Michael Tolosa , Chandrashekar Gurramkonda
发明人： Govind Rao , Yordan Kostov , Leah Tolosa , Kevin Tran , Monohar Pilli , Michael Tolosa , Chandrashekar Gurramkonda
IPC分类号： C12M1/00 , B01D15/38 , B01D15/36 , B01D15/32 , C12M1/40 , C07K1/36
摘要： A bioprocessing system for protein manufacturing from human blood is provided that is compact, integrated and suited for on-demand production and delivery of therapeutic proteins to patients. The patient's own blood can be used as the source of cell extracts for the production of the therapeutic proteins.

7. 发明授权

US08512334B2 Nanosecond pulsed electric field parameters for destroying tumors with a single treatment 有权
标题翻译：用单次处理破坏肿瘤的纳秒脉冲电场参数
公开(公告)号：US08512334B2
公开(公告)日：2013-08-20
申请号：US12722441
申请日：2010-03-11
申请人： Richard Lee Nuccitelli , Pamela Nuccitelli , Saleh Sheikh , Kevin Tran , Brian Athos , Mark Kreis
发明人： Richard Lee Nuccitelli , Pamela Nuccitelli , Saleh Sheikh , Kevin Tran , Brian Athos , Mark Kreis
IPC分类号： A61B18/18
CPC分类号： A61B18/14 , A61B18/1206 , A61B18/1477 , A61B2018/00291 , A61B2018/00452 , A61B2018/00577 , A61B2018/00726 , A61B2018/126 , A61B2018/1425 , A61B2018/143 , A61B2018/1467
摘要： Nanosecond pulsed electric field (nsPEF) parameters for destroying tumors with a single treatment are described. A nsPEF generator may be used with an electrode assembly to apply the pulses to one or more tumors where the parameters for the nsPEF are optimized for treating such tumors.
摘要翻译：描述了用单次处理破坏肿瘤的纳秒脉冲电场（nsPEF）参数。 nsPEF发生器可以与电极组件一起使用以将脉冲施加到一个或多个肿瘤，其中nsPEF的参数被优化用于治疗这样的肿瘤。

8. 发明授权

US06323704B1 Multiple voltage compatible I/O buffer 有权
标题翻译：多电压兼容I / O缓冲器
公开(公告)号：US06323704B1
公开(公告)日：2001-11-27
申请号：US09633948
申请日：2000-08-08
申请人： Perry H. Pelley , Kevin Tran
发明人： Perry H. Pelley , Kevin Tran
IPC分类号： H03K300
CPC分类号： H03K19/018528 , H03K19/00315
摘要： Input and output buffer circuitry (12, 14, 16) is provided which are compatible with busses operating at different voltage levels. The buffer circuitry is self-configuring based on the type of bus to which it is coupled. The buffer circuitry includes voltage level detect circuitry (20) and pad level detect circuitry (28) which can reconfigure driver (34, 54) and level shifter circuits (24, 26) in order to protect the switching devices of the buffers.
摘要翻译：提供与在不同电压电平下工作的总线兼容的输入和输出缓冲器电路（12,14,16）。缓冲电路基于与其耦合的总线类型进行自配置。缓冲电路包括可重新配置驱动器（34,54）和电平移位器电路（24,26）的电压电平检测电路（20）和焊盘电平检测电路（28），以保护缓冲器的开关装置。

9. 发明授权

US08321658B2 Method and system for iSCSI boot in which an iSCSI client loads boot code from a host bus adapter and/or network interface card 失效
标题翻译： iSCSI引导的方法和系统，其中iSCSI客户端从主机总线适配器和/或网络接口卡加载引导代码
公开(公告)号：US08321658B2
公开(公告)日：2012-11-27
申请号：US12826075
申请日：2010-06-29
申请人： Uri El Zur , Kan Frankie Fan , Murali Rajagopal , Kevin Tran
发明人： Uri El Zur , Kan Frankie Fan , Murali Rajagopal , Kevin Tran
IPC分类号： G06F15/177
CPC分类号： G06F9/4416
摘要： Certain aspects of a method for iSCSI boot may include loading boot BIOS code from a host bus adapter or a network interface controller (NIC) by an iSCSI client device. A connection may be established to an iSCSI target by the iSCSI client device after loading the boot BIOS code. The boot BIOS code may be chained to at least one interrupt handler over iSCSI protocol. An operating system may be remotely booted from the iSCSI target by the iSCSI client device based on chaining the interrupt handler. An Internet protocol (IP) address and/or location of the iSCSI target may be received. At least one iSCSI connection may be initiated to the iSCSI target based on chaining at least one interrupt handler. The iSCSI target may be booted in real mode if at least one master boot record is located in the memory.
摘要翻译： iSCSI引导方法的某些方面可能包括通过iSCSI客户端设备从主机总线适配器或网络接口控制器（NIC）加载引导BIOS代码。在加载引导BIOS代码之后，iSCSI客户端设备可以建立到iSCSI目标的连接。引导BIOS代码可以通过iSCSI协议链接至少一个中断处理程序。基于链接中断处理程序，iSCSI客户端设备可以从iSCSI目标远程启动操作系统。可以接收iSCSI目标的因特网协议（IP）地址和/或位置。至少一个iSCSI连接可以基于链接至少一个中断处理程序发起到iSCSI目标。如果至少有一个主引导记录位于存储器中，iSCSI目标可能会以实模式引导。

10. 发明授权

US07747847B2 Method and system for iSCSI boot in which an iSCSI client loads boot code from a host bus adapter and/or network interface card 有权
标题翻译： iSCSI引导的方法和系统，其中iSCSI客户端从主机总线适配器和/或网络接口卡加载引导代码
公开(公告)号：US07747847B2
公开(公告)日：2010-06-29
申请号：US11389980
申请日：2006-03-27
申请人： Uri El Zur , Kan Frankie Fan , Murali Rajagopal , Kevin Tran
发明人： Uri El Zur , Kan Frankie Fan , Murali Rajagopal , Kevin Tran
IPC分类号： G06F15/177
CPC分类号： G06F9/4416
摘要： Certain aspects of a method for iSCSI boot may include loading boot BIOS code from a host bus adapter or a network interface controller (NIC) by an iSCSI client device. A connection may be established to an iSCSI target by the iSCSI client device after loading the boot BIOS code. The boot BIOS code may be chained to at least one interrupt handler over iSCSI protocol. An operating system may be remotely booted from the iSCSI target by the iSCSI client device based on chaining the interrupt handler. An Internet protocol (IP) address and/or location of the iSCSI target may be received. At least one iSCSI connection may be initiated to the iSCSI target based on chaining at least one interrupt handler. The iSCSI target may be booted in real mode if at least one master boot record is located in the memory.
摘要翻译： iSCSI引导方法的某些方面可能包括通过iSCSI客户端设备从主机总线适配器或网络接口控制器（NIC）加载引导BIOS代码。在加载引导BIOS代码之后，iSCSI客户端设备可以建立到iSCSI目标的连接。引导BIOS代码可以通过iSCSI协议链接至少一个中断处理程序。基于链接中断处理程序，iSCSI客户端设备可以从iSCSI目标远程启动操作系统。可以接收iSCSI目标的因特网协议（IP）地址和/或位置。至少一个iSCSI连接可以基于链接至少一个中断处理程序发起到iSCSI目标。如果至少有一个主引导记录位于存储器中，iSCSI目标可能会以实模式引导。

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