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1. 发明申请

US20060259745A1 Processor having efficient function estimate instructions 失效
标题翻译：处理器具有有效的功能估计指令
公开(公告)号：US20060259745A1
公开(公告)日：2006-11-16
申请号：US11127848
申请日：2005-05-12
申请人： Sang Dhong , Gordon Fossum , Harm Hofstee , Brad Michael , Silvia Mueller , Hwa-Joon Oh
发明人： Sang Dhong , Gordon Fossum , Harm Hofstee , Brad Michael , Silvia Mueller , Hwa-Joon Oh
IPC分类号： G06F9/44
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： A preferred embodiment of the present invention provides a method, computer program product, and processor design for supporting high-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, a preferred embodiment of the present invention incurs significantly less overhead than would specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：本发明的优选实施例提供了一种用于支持高精度浮点函数估计的方法，计算机程序产品和处理器设计，其分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，本发明的优选实施例显着减少开销，同时仍保持均匀的FPU等待时间，这允许更简单的控制逻辑。

2. 发明申请

US20060101107A1 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效
标题翻译：用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置
公开(公告)号：US20060101107A1
公开(公告)日：2006-05-11
申请号：US10982110
申请日：2004-11-05
申请人： Sang Dhong , Harm Hofstee , Christian Jacobi , Silvia Mueller , Hwa-Joon Oh
发明人： Sang Dhong , Harm Hofstee , Christian Jacobi , Silvia Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

3. 发明申请

US20060179176A1 System and method for a memory with combined line and word access 有权
标题翻译：具有组合线和字访问的存储器的系统和方法
公开(公告)号：US20060179176A1
公开(公告)日：2006-08-10
申请号：US11050040
申请日：2005-02-03
申请人： Sang Dhong , Brian Flachs , Harm Hofstee , Osamu Takahashi
发明人： Sang Dhong , Brian Flachs , Harm Hofstee , Osamu Takahashi
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/1626 , G06F13/1663
摘要： A system and method for a processor with memory with combined line and word access are presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.
摘要翻译：提出了一种具有组合线和字访问的存储器的处理器的系统和方法。系统执行窄读/写存储器访问，并使用多路复用器和锁存器对同一存储体进行宽读/写存储器访问以指导数据。该系统使用窄读/写存储器访问处理16字节加载/请求请求，并使用宽读/写存储器访问处理128字节的DMA和指令提取请求。在DMA请求期间，系统在一个指令周期内将16个DMA操作写入/读取存储器。通过这样做，内存可用于在十五个其他指令周期内处理加载/存储或指令提取请求。

4. 发明申请

US20050055185A1 Random carry-in for floating-point operations 有权
标题翻译：随机进位浮点运算
公开(公告)号：US20050055185A1
公开(公告)日：2005-03-10
申请号：US10971851
申请日：2004-10-22
申请人： Sang Dhong , Harm Hofstee , Kevin Nowka , Stephen Posluszny , Joel Silberman
发明人： Sang Dhong , Harm Hofstee , Kevin Nowka , Stephen Posluszny , Joel Silberman
IPC分类号： G06F7/38 , G06F7/42 , G06F7/485 , G06F7/499 , G06F17/10
CPC分类号： G06F7/485 , G06F7/49947
摘要： A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.
摘要翻译：一种用于对浮点操作数进行相加和相乘以产生固定大小的尾数结果的方法和装置。根据本加法，第一浮点数操作数的尾数根据相对操作数指数信息移位。接下来，将第一操作数尾数添加到第二操作数尾数。所述添加步骤包括用随机生成的进位位替换第一操作数尾数的最不重要的非重叠部分。根据乘法方法，从一对浮点运算符尾数生成部分乘积数组。接下来，在将部分乘积阵列压缩为压缩尾数结果之前，将部分乘积阵列的低阶位部分替换为随机生成的进位值。

5. 发明申请

US20070040620A1 Method of functionality testing for a ring oscillator 失效
标题翻译：环形振荡器的功能测试方法
公开(公告)号：US20070040620A1
公开(公告)日：2007-02-22
申请号：US11204408
申请日：2005-08-16
申请人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
发明人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K5/133
摘要： A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input. The embodiment further comprises detecting the response to the applied first and second test bit signals at the output of the second inverter, and using the detected responses in providing an evaluation of functionality of the ring oscillator.
摘要翻译：提供了一种用于测试环形振荡器的逻辑功能和电连续性的方法和装置，该环形振荡器包括连接形成闭环的奇数个反相器。在该方法和装置中，通过环形振荡器强制已知的值，以测试其完整的电路路径。因此，提供了环形振荡器的功能的低开销确定性测试。在本发明的有用实施例中，提供了一种用于测试环形振荡器中的功能和电连续性的方法，其中第一测试装置插入在第一反相器的输入端和相邻的第二反相器的输出之间。然后操作第一测试装置以将第一和第二测试位作为输入测试信号施加到第一反相器输入。该实施例还包括检测在第二反相器的输出处对所施加的第一和第二测试位信号的响应，并且使用检测到的响应来提供环形振荡器的功能性的评估。

6. 发明申请

US20060031836A1 Hierarchical management for multiprocessor system with real-time attributes 失效
标题翻译：具有实时属性的多处理器系统的分层管理
公开(公告)号：US20060031836A1
公开(公告)日：2006-02-09
申请号：US10912481
申请日：2004-08-05
申请人： Jeffrey Brown , Michael Day , Harm Hofstee , Charles Johns , James Kahle , Michael Wang
发明人： Jeffrey Brown , Michael Day , Harm Hofstee , Charles Johns , James Kahle , Michael Wang
IPC分类号： G06F9/46
CPC分类号： G06F1/3203
摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.
摘要翻译：本发明提供用于控制元件的功耗。第一个功率控制命令由该元件的软件发出。确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。该软件是实时软件，软件还设置了最低限度可接受的活动控制状态。通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。

7. 发明申请

US20050268048A1 System and method for using a plurality of heterogeneous processors in a common computer system 审中-公开
标题翻译：在普通计算机系统中使用多个异构处理器的系统和方法
公开(公告)号：US20050268048A1
公开(公告)日：2005-12-01
申请号：US11171757
申请日：2005-06-30
申请人： Harm Hofstee , Charles Johns , James Kahle
发明人： Harm Hofstee , Charles Johns , James Kahle
IPC分类号： G06F15/16 , G06F9/44 , G06F9/50 , G06F15/177 , G06F15/80 , H04L29/06 , H04L29/08 , G06F13/00
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A system for using a plurality of heterogeneous processors in a common computer system is presented. Each processor type in the heterogeneous group handles a particular instruction set. The processors share a common memory using a common bus. In one embodiment, one of the processor types accesses the memory using DMA instructions. In another embodiment, a cache for each type of processor is stored in the common memory pool. In one embodiment, one or more PowerPC processors shares a memory with one or more Synergistic Processing Complex (SPC). A common table is used to track and maintain memory for the various processors.
摘要翻译：提出了一种在普通计算机系统中使用多个异构处理器的系统。异构组中的每个处理器类型处理特定的指令集。处理器使用公共总线共享共享内存。在一个实施例中，处理器类型之一使用DMA指令访问存储器。在另一个实施例中，用于每种类型的处理器的高速缓存存储在公共存储器池中。在一个实施例中，一个或多个PowerPC处理器与一个或多个协同处理复合体（SPC）共享存储器。通用表用于跟踪和维护各种处理器的内存。

8. 发明申请

US20050080998A1 Method and apparatus for coherent memory structure of heterogeneous processor systems 失效
标题翻译：异构处理器系统的相干存储器结构的方法和装置
公开(公告)号：US20050080998A1
公开(公告)日：2005-04-14
申请号：US10682386
申请日：2003-10-09
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong
IPC分类号： G06F12/08
CPC分类号： G06F12/0835
摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.
摘要翻译：公开了与非均匀处理单元结合操作的一致的缓存系统。一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

9. 发明申请

US20050021944A1 Security architecture for system on chip 有权
标题翻译：片上系统的安全架构
公开(公告)号：US20050021944A1
公开(公告)日：2005-01-27
申请号：US10601374
申请日：2003-06-23
申请人： David Craft , Michael Day , Harm Hofstee , Charles Johns , John Liberty
发明人： David Craft , Michael Day , Harm Hofstee , Charles Johns , John Liberty
IPC分类号： G06F12/14 , G06F21/22 , G06F21/24 , G09C1/00 , H04L9/08 , H04L9/00
CPC分类号： G06F21/53 , H04L9/3226 , H04L2209/56
摘要： The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.
摘要翻译：本发明提供了验证代码和/或数据并提供受保护的环境以供执行。本发明提供了用于对代码或数据的认证的动态分区和分区本地存储。本地商店被划分成一个隔离和非隔离的部分。代码或数据被加载到隔离的部分。代码或数据在本地存储的隔离部分进行身份验证。认证后，执行代码。在执行之后，附着的处理器单元的隔离区域内的存储器被擦除，并且附加的处理器单元对本地存储器内的隔离部分进行分区。

10. 发明申请

US20060220753A1 Oscillator array with row and column control 有权
标题翻译：具有行和列控制的振荡器阵列
公开(公告)号：US20060220753A1
公开(公告)日：2006-10-05
申请号：US11095895
申请日：2005-03-31
申请人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
发明人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
IPC分类号： H03K3/03
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.
摘要翻译：提供了一种电路拓扑结构，可用于创建由通用控制输入确定的不同频率运行的单独调谐的振荡器阵列，以及易于管理的多个组件的设计尺寸变化。提供了一列列和列排列的振荡器阵列。列中的每个振荡器都基于列中的其他振荡器是独特的，基于振荡器和扇出的级数，使得每个振荡器将以唯一的频率工作。阵列中不同列的振荡器可能会通过对这些振荡器的选择的共同设置以及列中的振荡器的物理顺序而不同，以进一步降低注入锁定的可能性。基本延迟单元为每列振荡器提供选择，使得每列可被编程为以与其邻居不同的频率工作。

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