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1. 发明申请

US20070186135A1 Processor system and methodology with background error handling feature 审中-公开
标题翻译：具有背景错误处理功能的处理器系统和方法
公开(公告)号：US20070186135A1
公开(公告)日：2007-08-09
申请号：US11351121
申请日：2006-02-09
申请人： Brian Flachs , H. Hofstee , John Liberty , Brad Michael
发明人： Brian Flachs , H. Hofstee , John Liberty , Brad Michael
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A processor system is disclosed that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. ECC hardware circuitry provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The disclosed methodology permits the detection and correction of soft single bit errors read from local memory in-line while using read modify write DMA circuit logic to correct local memory data. The disclosed methodology provides local memory data error detection and correction in a background memory scrub process without the need for additional in-line data logic.
摘要翻译：公开了一种在存储器管理电路内集成纠错码（ECC）检测和校正硬件的处理器系统。 ECC硬件电路提供与存储器数据读取和写入相结合的ECC数据位的检测，校正和生成。所公开的方法允许检测和校正从本地存储器在线读取的软单比特错误，同时使用读修改写DMA电路逻辑来校正本地存储器数据。所公开的方法在后台存储器擦除过程中提供本地存储器数据错误检测和校正，而不需要额外的在线数据逻辑。

2. 发明申请

US20070043926A1 System and method for limiting the size of a local storage of a processor 失效
标题翻译：用于限制处理器的本地存储器的大小的系统和方法
公开(公告)号：US20070043926A1
公开(公告)日：2007-02-22
申请号：US11208376
申请日：2005-08-19
申请人： Adam Burns , Michael Day , Brian Flachs , H. Hofstee , Charles Johns , John Liberty
发明人： Adam Burns , Michael Day , Brian Flachs , H. Hofstee , Charles Johns , John Liberty
IPC分类号： G06F12/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system and method for limiting the size of a local storage of a processor are provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译：提供了用于限制处理器的本地存储器的大小的系统和方法。与用于设置本地存储大小限制的处理器相关联地提供设施。该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为用于访问本地存储。

3. 发明授权

US07730279B2 System for limiting the size of a local storage of a processor 失效
标题翻译：用于限制处理器的本地存储器的大小的系统
公开(公告)号：US07730279B2
公开(公告)日：2010-06-01
申请号：US12429676
申请日：2009-04-24
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
IPC分类号： G06F12/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译：提供了用于限制处理器的本地存储器的大小的系统。与用于设置本地存储大小限制的处理器相关联地提供设施。该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为用于访问本地存储。

4. 发明申请

US20090204781A1 System for Limiting the Size of a Local Storage of a Processor 失效
标题翻译：限制处理器本地存储大小的系统
公开(公告)号：US20090204781A1
公开(公告)日：2009-08-13
申请号：US12429676
申请日：2009-04-24
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
IPC分类号： G06F12/00 , G06F3/00 , G06F12/02 , G06F15/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译：提供了用于限制处理器的本地存储器的大小的系统。与用于设置本地存储大小限制的处理器相关联地提供设施。该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为用于访问本地存储。

5. 发明授权

US07533238B2 Method for limiting the size of a local storage of a processor 失效
标题翻译：用于限制处理器的本地存储器的大小的方法
公开(公告)号：US07533238B2
公开(公告)日：2009-05-12
申请号：US11208376
申请日：2005-08-19
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
IPC分类号： G06F12/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译：提供了一种用于限制处理器的本地存储器的大小的方法。与用于设置本地存储大小限制的处理器相关联地提供设施。该设施是一个特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化上下文切换时，操作系统设置存储在本地存储限制寄存器中的值在处理器中。当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为用于访问本地存储。

6. 发明申请

US20060224869A1 Combination of forwarding/bypass network with history file 审中-公开
标题翻译：转发/旁路网络与历史文件的组合
公开(公告)号：US20060224869A1
公开(公告)日：2006-10-05
申请号：US11095908
申请日：2005-03-31
申请人： Brian Flachs , Brad Michael
发明人： Brian Flachs , Brad Michael
IPC分类号： G06F9/44
CPC分类号： G06F9/3842 , G06F9/3863 , G06F9/3867
摘要： An apparatus, a method, and a processor are provided for recovering the correct state of processor instructions in a processor. This apparatus contains a pipeline of latches, a register file, and a replay loop. The replay loop repairs incorrect results and inserts the repaired results back into the pipeline. A state machine detects incorrect results within the pipeline and sends the incorrect results to the replay loop. A correction module on the replay loop repairs the incorrect results and transmits the repaired results back into the pipeline. When an incorrect result enters the replay loop, a flush operation: ceases other operations within the pipeline; flushes the rest of the data results in the pipeline to the replay loop; opens the pipeline for the repaired results to be inserted; and eliminates any operations within the processor that would utilize the incorrect results.
摘要翻译：提供了一种用于在处理器中恢复处理器指令的正确状态的装置，方法和处理器。该设备包含一个锁存器流水线，一个寄存器文件和一个重放循环。重播循环修复不正确的结果，并将修复的结果插入管道。状态机在管道中检测不正确的结果，并将不正确的结果发送到重放循环。重播循环上的校正模块修复错误的结果，并将修复的结果发送回管道。当不正确的结果进入重放循环时，刷新操作：停止管道内的其他操作; 将流水线中的其余数据结果刷新到重放循环; 打开要插入的修复结果的管道; 并消除处理器内利用错误结果的任何操作。

7. 发明申请

US20060179277A1 System and method for instruction line buffer holding a branch target buffer 审中-公开
标题翻译：用于指示行缓冲器的系统和方法，保持分支目标缓冲区
公开(公告)号：US20060179277A1
公开(公告)日：2006-08-10
申请号：US11052502
申请日：2005-02-04
申请人： Brian Flachs , Brad Michael
发明人： Brian Flachs , Brad Michael
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30047 , G06F9/3804 , G06F9/3814
摘要： A system and method that maintains a relatively small Instruction Load Buffer (ILB) is maintained for scheduling instructions. Instructions are sent from Local Store (LS) to the ILB using either an inline prefetcher or a branch table buffer loader. In one embodiment, the prefetcher is a hardware-based prefetcher that fetches, in address order, the next instructions likely to be scheduled. In one embodiment, the predicted branch instructions are loaded as a result of a software program, such as a dispatcher, issuing a “load branch table buffer (loadbtb)” instruction. Predicted branch instructions are loaded in one area of the ILB and inline instructions are loaded in another area of the ILB. In one embodiment, the loadbtb loads the instruction line that includes the predicted branch target address as well as the instruction line that immediately follows the instruction line with the predicted branch target address.
摘要翻译：维护相对较小的指令加载缓冲器（ILB）的系统和方法被维护用于调度指令。使用内联预取器或分支表缓冲区加载器将本地存储（LS）发送到ILB。在一个实施例中，预取器是基于硬件的预取器，其以地址顺序提取可能被调度的下一个指令。在一个实施例中，作为诸如调度器的软件程序的结果，预测的分支指令被加载，发出“加载分支表缓冲器（loadbtb）”指令。预测的分支指令被加载到ILB的一个区域中，并且内联指令被加载到ILB的另一个区域中。在一个实施例中，loadbtb将包含预测的分支目标地址的指令行以及与预测的分支目标地址紧接在指令行之后的指令行一起加载。

8. 发明授权

US08782381B2 Dynamically rewriting branch instructions in response to cache line eviction 有权
标题翻译：动态地重写分支指令以响应缓存线驱逐
公开(公告)号：US08782381B2
公开(公告)日：2014-07-15
申请号：US13444890
申请日：2012-04-12
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4442 , G06F9/3806 , G06F12/0875 , G06F12/12
摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.
摘要翻译：提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。确定当前高速缓存行是否将从指令高速缓存中逐出。处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

9. 发明授权

US08627051B2 Dynamically rewriting branch instructions to directly target an instruction cache location 有权
标题翻译：动态地重写分支指令直接指向指令高速缓存位置
公开(公告)号：US08627051B2
公开(公告)日：2014-01-07
申请号：US13442919
申请日：2012-04-10
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F9/3806 , G06F12/0875
摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.
摘要翻译：提供了用于在代码的一部分中动态地重写分支指令的机制。这些机制在代码的一部分中执行分支指令。这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，这些机制将代码部分的执行重定向到指令高速缓存运行时系统。

10. 发明申请

US20110321021A1 Arranging Binary Code Based on Call Graph Partitioning 有权
标题翻译：基于调用图划分二进制代码
公开(公告)号：US20110321021A1
公开(公告)日：2011-12-29
申请号：US12823244
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.
摘要翻译：提供了用于布置二进制代码以减少指令高速缓存冲突未命中的机制。这些机制产生一部分代码的调用图。调用图中的节点和边被加权以生成加权调用图。然后根据权重，调用图的节点之间的亲和度和数据处理系统的指令高速缓存中的高速缓存行的大小来分配加权调用图，使得与一个或多个节点的子集相关联的二进制代码调用图被组合到基于分区的各个高速缓存行。然后输出与划分的调用图对应的二进制代码，以在计算设备中执行。

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