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1. 发明授权

US07405685B2 Negative contributive offset compensation in a transmit buffer utilizing inverse clocking 有权
标题翻译：使用反向时钟的发送缓冲器中的负贡献偏移补偿
公开(公告)号：US07405685B2
公开(公告)日：2008-07-29
申请号：US11178993
申请日：2005-07-11
申请人： Sameh S. Rezeq , Dirk Leipold , Robert B. Staszewski , Chih-Ming Hung
发明人： Sameh S. Rezeq , Dirk Leipold , Robert B. Staszewski , Chih-Ming Hung
IPC分类号： H03M3/00
CPC分类号： H03F1/0205 , H03F1/3241 , H03F2200/331 , H03F2200/375 , H03M3/356 , H03M3/50 , H03M7/3026 , H03M7/3037 , H04L27/368
摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
摘要翻译：一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。来自Σ-Δ调制器的正输出的处理方式与负输出不同。与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。时钟的非反相版本与正输出一起使用，反向时钟与负输出一起使用。使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。结果是具有零偏移的偏移补偿RF输出信号。

2. 发明授权

US07006813B2 Efficient charge transfer using a switched capacitor resistor 有权
公开(公告)号：US07006813B2
公开(公告)日：2006-02-28
申请号：US10147784
申请日：2002-05-16
申请人： Robert B. Staszewski , Khurram Muhammad , Chih-Ming Hung , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Chih-Ming Hung , Dirk Leipold
IPC分类号： H04B1/26
CPC分类号： H03D7/125 , H04B1/1036
摘要： The application of a non-zero voltage offset to rotating capacitors 1111 and 1112 permit the use of a single positive voltage supply. However, the precharging of the rotating capacitors 1111 and 1112 is power inefficient. A power efficient and low-noise precharging operation is realized through the sharing of the charge on a feedback capacitor 1075 and 1080 that is significantly larger than the rotating capacitors 1111. Once a precharging operation is complete, the charge on the feedback capacitor 1075 and 1080 is refreshed from its residual charge level (rather than zero charge level) to a desired charge level.

3. 发明授权

US06734741B2 Frequency synthesizer with digitally-controlled oscillator 有权
公开(公告)号：US06734741B2
公开(公告)日：2004-05-11
申请号：US10006607
申请日：2001-11-30
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
IPC分类号： H03L700
CPC分类号： H03C3/0975 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0966 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/50 , H04L7/0029
摘要： A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.

4. 发明授权

US07463869B2 Low noise high isolation transmit buffer gain control mechanism 有权
标题翻译：低噪声高隔离传输缓冲器增益控制机制
公开(公告)号：US07463869B2
公开(公告)日：2008-12-09
申请号：US11115815
申请日：2005-04-26
申请人： Chih-Ming Hung , Francis P. Cruise , Dirk Leipold , Robert B. Staszewski
发明人： Chih-Ming Hung , Francis P. Cruise , Dirk Leipold , Robert B. Staszewski
IPC分类号： H04B1/04
CPC分类号： H04B1/0483 , H03F1/3241 , H03F1/3294 , H03F3/191 , H03F2200/331
摘要： A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.
摘要翻译：一种低噪声，高隔离，全数字发送缓冲增益控制机制的新型设备。增益控制方案在全数字直接数/频幅度转换器（DRAC）的上下文中呈现，该转换器有效地结合了上变频，I和Q组合，D / A转换，滤波，缓冲和 RF输出幅度控制成单个电路。发送缓冲器构造为NMOS开关阵列。每个NMOS开关的控制逻辑包括一个通门型AND门，其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。通过在CMOS工艺中实现时，通过识别伪E类预功率放大器（PPA）所遭受的损伤来实现功率控制。首先，阵列的NMOS开关具有大的导通电阻，因此当输入波形为高时，只能从RF扼流圈画出有限的电流。在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制，并允许控制RF输出功率的全数字方法。

5. 发明授权

US06791422B2 Frequency synthesizer with digitally-controlled oscillator 有权
标题翻译：具有数字控制振荡器的频率合成器
公开(公告)号：US06791422B2
公开(公告)日：2004-09-14
申请号：US10679792
申请日：2003-10-06
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
IPC分类号： H03L700
CPC分类号： H03C3/0975 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0966 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/50 , H04L7/0029
摘要： A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.
摘要翻译：基于频率合成器的发射机（10）包括具有各种电容器阵列的数字控制振荡器（DCO）的LC箱（12）。液相色谱箱12分为反映两种一般操作模式的两个主要组：采集和跟踪。第一组（过程/电压/温度和采集）最初初始化设置所需的中心振荡频率，而第二组（整数和分数跟踪）在实际操作期间精确地控制振荡频率。对于高精度输出，在整数跟踪控制器中使用动态元件匹配（DEM）来减少由非均匀电容值引起的非线性。此外，在获取所选择的信道之后，整数跟踪电容器阵列的优选范围可以用于调制。数字Σ-Δ调制器电路（50）响应错误字的分数位驱动电容器阵列（14d）。在模式开关上，累加误差被重新计算到相位重启值，以防止扰动。

6. 发明申请

US20070189417A1 PRECISE DELAY ALIGNMENT BETWEEN AMPLITUDE AND PHASE/FREQUENCY MODULATION PATHS IN A DIGITAL POLAR TRANSMITTER 有权
标题翻译：数字极性放大器中的幅度和相位/频率调制方式之间的精确延迟对准
公开(公告)号：US20070189417A1
公开(公告)日：2007-08-16
申请号：US11675565
申请日：2007-02-15
申请人： Khurram Waheed , Jayawardan Janardhanan , Sameh S. Rezeq , Robert B. Staszewski , Saket Jalan
发明人： Khurram Waheed , Jayawardan Janardhanan , Sameh S. Rezeq , Robert B. Staszewski , Saket Jalan
IPC分类号： H04L27/04 , H04L7/00
CPC分类号： H04L27/368 , H03C5/00 , H04L7/0029 , H04L7/0041 , H04L7/005 , H04L7/0079 , H04L7/02
摘要： A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.
摘要翻译：数字极性发射机的幅度和相位/频率调制路径之间的延迟对准的新型装置和方法。本发明提供了一种全数字延迟对准机制，其通过考虑发射机的数字电路模块中的处理延迟以及通过使用分布在几个时钟域上的可编程延迟元件来实现比纳秒对准更好的方法。分接延迟线补偿模拟元件（如DCO，分频器，四通道开关，缓冲器，电平移位器和数字预功率放大器（DPA））中的传播和稳定延迟。提供了一种信号相关机制，其中来自要匹配的幅度和相位/频率调制路径的数据首先被内插，然后进行交叉相关，以获得比时钟域更好的比较。在发射机的ADPLL部分内，使用多个时钟域，抽头延迟线和时钟调整电路来证明ADPLL中的参考点和直接点注入点的精确对准。

7. 发明授权

US09020454B2 Linearization and calibration predistortion of a digitally controlled power amplifier 有权
标题翻译：数字控制功率放大器的线性化和校准预失真
公开(公告)号：US09020454B2
公开(公告)日：2015-04-28
申请号：US13481450
申请日：2012-05-25
申请人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
发明人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译：用于执行预失真校准以补偿DPA和PA电路中的非线性的数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的装置和方法。预失真查询表（LUT）存储在被输入到数字 - 频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。在半双工操作期间TX突发期间通常不工作的片上接收器解调RF PA输出并使用数字I / Q RX输出来执行TX预失真表的校准。将RF输出信号的样本提供给接收器链。当PA（DPA）代码正在增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值，可以计算预失真表。

8. 发明申请

US20100188148A1 PREDISTORTION MECHANISM FOR COMPENSATION OF TRANSISTOR SIZE MISMATCH IN A DIGITAL POWER AMPLIFIER 审中-公开
标题翻译：用于补偿数字功率放大器中晶体管尺寸误差的预测机制
公开(公告)号：US20100188148A1
公开(公告)日：2010-07-29
申请号：US12359613
申请日：2009-01-26
申请人： Jaimin A. Mehta , Sameh S. Rezeq , Manouchehr Entezari , Robert B. Staszewski
发明人： Jaimin A. Mehta , Sameh S. Rezeq , Manouchehr Entezari , Robert B. Staszewski
IPC分类号： H03F1/26
CPC分类号： H03F1/3247 , H03F1/30
摘要： A novel and useful apparatus for and method of predistortion compensation of device (e.g., transistor) mismatch in a digital power amplifier (DPA). The device mismatch predistortion mechanism of the present invention addresses the problem of matching between two types of binary weighted transistors, whereby mismatched transistors cause degradation in wideband noise. The invention provides a digital predistortion mechanism which functions to pre-distort the mismatch ratio based on a data table calculated a priori enabling a polar transmitter to meet output spectrum and error vector magnitude (EVM) requirements of the particular modern wideband wireless standard, such as GSM, 3G WCDMA, etc.
摘要翻译：一种用于数字功率放大器（DPA）中的器件（例如，晶体管）失配的预失真补偿的新颖有用的装置和方法。本发明的器件失配预失真机制解决了两种二进制加权晶体管之间的匹配问题，由此失配的晶体管导致宽带噪声的降低。本发明提供了一种数字预失真机制，其用于基于先前计算的数据表来预失真失配比，使得极性发射机能够满足特定现代宽带无线标准的输出频谱和误差矢量幅度（EVM）要求，例如 GSM，3G WCDMA等

9. 发明申请

US20120263256A1 LINEARIZATION OF A TRANSMIT AMPLIFIER 审中-公开
标题翻译：发射放大器的线性化
公开(公告)号：US20120263256A1
公开(公告)日：2012-10-18
申请号：US13481450
申请日：2012-05-25
申请人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
发明人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
IPC分类号： H04L25/49
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译：用于执行预失真校准以补偿DPA和PA电路中的非线性的数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的装置和方法。预失真查询表（LUT）存储在被输入到数字 - 频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。在半双工操作期间TX突发期间通常不工作的片上接收器解调RF PA输出并使用数字I / Q RX输出来执行TX预失真表的校准。将RF输出信号的样本提供给接收器链。当PA（DPA）代码正在增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值，可以计算预失真表。

10. 发明授权

US08195103B2 Linearization of a transmit amplifier 有权
标题翻译：发射放大器的线性化
公开(公告)号：US08195103B2
公开(公告)日：2012-06-05
申请号：US11675582
申请日：2007-02-15
申请人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
发明人： Khurram Waheed , Robert B. Staszewski , Sameh S. Rezeq , Oren E. Eliezer
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H04B2001/0425
摘要： A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp. While the digitally-controlled PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.
摘要翻译：一种数字控制的预功率放大器（DPA）和RF功率放大器（PA）的线性化的新型装置和方法。该机制可用于执行预失真校准，以补偿DPA和PA电路中的非线性。预失真查询表（LUT）存储在被输入到数字到频率转换器（DFC），DPA和PA之前施加到TX数据的测量失真补偿数据。本发明的机制利用在半双工操作期间TX突发期间通常不活动的片上接收机来解调RF PA输出并使用数字I / Q RX输出来执行TX的校准预失真表。受控RF耦合用于向接收机链提供RF输出信号的采样。预失真LUT的内容通常在PA上电或下降斜坡期间更新。当数字控制的PA（DPA）码增加（或减小）时，恢复的I / Q采样的振幅和相位用于确定AM / AM和AM / PM预失真的瞬时值，可以计算对预失真表的更新。

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